SLVU405 Datasheet, PDF (2/14 Pages) Texas Instruments – TPS7A30-49EVM-567

Introduction
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1 Introduction
The Texas Instruments TPS7A30-49EVM-567 EVM helps designers evaluate the operation and
performance of the TPS7A3001 and/or the TPS7A4901 LDO regulator for possible use in their circuit
applications. This particular EVM configuration is preconfigured to output –15 Vdc and +15 Vdc for ease of
demonstration in certain standard industrial applications, e.g., requiring positive and negative voltages to
power an operational amplifier-based, signal-conditioning circuitry. Alternatively, each LDO channel can be
adjusted individually to any output voltage between 1.2 V and 33 V (negative and positive, respectively) as
required by only changing a resistor value in accordance with the given equation. The TPS7A3001 can
supply up to 200-mA-rated load current and the TPS7A4901 can supply up to 150 mA each using the
MSOP-8, PowerPAD™ package. Both circuits have been optimized for ac performance including PSRR
and load transient response using capacitors rated over the full voltage range of each regulator.
2 Setup
This section describes the jumpers and connectors on the EVM as well as how to properly connect, set
up, and use the TPS7A30-49EVM-567.
2.1 Negative Voltage Input/Output Connectors and Jumper Descriptions For TPS7A3001
LDO Circuit
• J1 (–VIN) – The negative input supply voltage connector. Twist the negative input lead and ground
lead, and keep them as short as possible to minimize EMI transmission. Additional bulk aluminum
electrolytic capacitance must be added/connected between J1 and J2 if the supply leads are greater
than 6 inches. An additional 47-µF or greater capacitor improves the transient response and reduces
parasitic ringing due to long wire connections.
• J2 (GND) – Ground-return connection for the negative input power supply.
• J3 (EN) – Negative voltage, output enable. To enable the negative voltage output, connect a jumper
between ON, pin 1 to EN, pin 2. To disable the negative voltage output, connect the jumper between
EN, center pin 2 and OFF, pin 3.
• J4 (–VOUT) – Negative voltage, output connector.
• J5 (GND) – Negative voltage output ground-return connector.
2.2 Positive Voltage Input/Output Connectors and Jumper Descriptions fo the
TPS7A4901 LDO Circuit
• J6 (+VIN) – The positive input supply voltage connector. Twist the positive input lead and ground lead,
and keep them as short as possible to minimize EMI transmission. Additional bulk aluminum
electrolytic capacitance must be added/connected between J6 and J7 if the supply leads are greater
than 6 inches. An additional 47-µF or greater capacitor improves the transient response and reduces
parasitic ringing due to long wire connections.
• J7 (GND) – Ground-return connection for the positive input power supply.
• J8 (EN) – Positive voltage, output enable. To enable the positive voltage output, connect a jumper
between ON, pin 1 to EN, pin 2. To disable the positive voltage output, connect the jumper between
EN, center pin 2 and OFF, pin 3.
• J9 (+VOUT) – Negative voltage, output connector.
• J10 (GND) – Positive voltage output ground-return connector.
2.3 Soldering Guidelines
Any solder re-work to modify the EVM for the purpose of repair or other application reasons must be
performed using a hot-air system to avoid damaging the integrated circuit (IC).
2
TPS7A30-49EVM-567
Copyright © 2010, Texas Instruments Incorporated
SLVU405 – August 2010