GC1012B_07 Datasheet, PDF (7/30 Pages) Texas Instruments – 3.3V DIGITAL TUNER CHIP

GC1012B 3.3V DIGITAL TUNER
SLWS138B
The chip will only drive these pins when CE is low and RE is high. If RE is held low, then the
interface will behave in the GC1012A mode, where CE is CS, and WE is R/W.
Control register addresses 12, 13, 14, and 15 are reserved to allow an external processor to read
output samples from the chip. Addresses 12 and 13 are the I-registers which store the16 bit in-phase part
of the output sample. Addresses 14 and 15 are the Q-registers which store the quadrature part. In the real
mode the I registers store the even-time output samples and the Q registers store the odd-time output
samples. Output ready and missed flags are provided in control register 9 in order to synchronize the storing
and reading of the output samples. An interrupt output pin is also provided on the chip which can be used
to interrupt the external processor when a new sample is ready. See the description of control register 9 in
Section 3.6 for more details. The setup, hold and pulse width requirements for control read or write
operations are given in Section 4.4.
Checksums are read from the chip during diagnostics using address 11. More details on the
diagnostic modes is given in Section 1.11.
Address 10 is used to generate a one-shot pulse on the OS output pin. This pulse can be used to
synchronize the output timing and/or frequency oscillators of multiple GC1012B chips.
The control interface also generates the chip’s internal sync strobes. The user may select to
synchronize the chip using an external sync strobe (SS), or use the chip’s internal sync counter. The internal
sync counter can be synchronized to SS, or left to free run (See SS_OFF in Section 3.2). The period of the
internal sync counter can be either 256 clocks or 2²⁰ clocks. The 256 clock period is intended to be used
for chip test purposes only. The internal sync counter is used during diagnostics to clear the data paths and
strobe the checksum generator. The internal sync counter can also be used to periodically re-synchronize
all of the counters in the chip during normal operating modes.
1.4 DIGITAL OSCILLATOR
The digital oscillator generates sine and cosine sequences which are used to mix the desired signal
down to zero frequency. The digital oscillator contains a 28 bit frequency register, a 28 bit frequency
accumulator, and a sine-cosine generator. The tuning frequency of the oscillator is set by loading a 28 bit
frequency word from the control registers into the frequency register. If the frequency register is set to the
word FREQ, then the tuning frequency will be: Frequency = ^S-----^a---^m-----^p-2--^l-₂^e---₈---^R----^a---^t--^e--FREQ . The tuning frequency
should be set to the middle of the desired output bandwidth.
The frequency word FREQ is stored into the control registers at control addresses 0,1,2 and 3. The
28 bit word is then transferred into the frequency register using one of the following methods:
(1) The frequency register is always loading (the frequency changes immediately as the
frequency word is loaded into the control registers).
(2) The frequency register is loaded when the user sets a control register bit.
(3) The frequency register is synchronously loaded when the accumulator sync strobe (AS) goes
low.
(4) The frequency register is synchronously loaded when the system sync strobe (SS) goes low.
Texas Instruments Incorporated
-3-
This document contains information which may be changed at any time without notice