GC1012B_07 Datasheet, PDF (5/30 Pages) Texas Instruments – 3.3V DIGITAL TUNER CHIP

GC1012B 3.3V DIGITAL TUNER
SLWS138B
GC1012B DATASHEET
1.0 FUNCTIONAL DESCRIPTION
Fabricated in high speed CMOS technology, the GC1012B chip is an all digital tuner which can
downconvert and band limit signals from wide band digitized sources. At full rate operation (100 MHz input
rate), the input bandwidth can be up to 50 MHz wide. Any signal within the input bandwidth can be
down-converted to zero frequency, low pass filtered, and output at a reduced sample rate. The chip’s output
can be formatted as either a complex data stream, or as a real data stream. The complex samples are
output at rates equal to F_O=F_CK/D, where F_O is the output rate, D is 1, 2, 4, 8, 16, 32 or 64 and F_CK is the
input sample (clock) rate. The real output rates are F_O=2F_CK/D for D equal to 2, 4, 8, 16, 32, or 64.
The signal is low pass filtered to remove out of band energy before the sample rate is decreased.
The filter’s out of band rejection is over 75 dB and its passband ripple is less than 0.2 dB peak to peak. The
passband of the output filter covers 80% of the output bandwidth.
The 28 bit accumulator in the chip’s digital oscillator circuit provides a tuning accuracy equal to the
input clock rate divided by 2²⁸. The tuning resolution at a clock rate of 50 MHz is less than 0.2 Hz giving a
tuning accuracy of +/- 0.1 Hz. The phase noise in the oscillator is low enough to provide a spur free dynamic
range of over 75 dB.
The chip’s output circuit allows the user to select a real or complex data output format, to select
spectral inversion, or to offset the output spectrum by half of the output sample rate. The output’s signal gain
can be adjusted in 0.03 dB steps. The word size of the output samples are either 10, 12, 14, or 16 bits.
On chip diagnostic circuits are provided to simplify system debug and maintenance.
The chip receives configuration and control information over a microprocessor compatible bus
consisting of an 8 bit data I/O port, a 4 bit address port, read and write strobes, and a control select strobe.
I and Q output registers can be read from the control port to allow an external processor to monitor
or process the chip’s output samples. These registers are valuable for monitoring the chip’s output power
in order to set and adjust gain levels.
1.1 KEY FEATURES
• 100 million samples per second input rate
• 0.1 Hz tuning resolution
• >75 dB dynamic range
• Programmable output bandwidth
• 12 bit inputs, 10, 12, 14, or 16 bit outputs
• Real or complex output formats
• Built in strobe/sync generator
• Symmetric rounding used throughout
• Gain adjust in 0.03 dB steps
• Microprocessor interface for control,
output, and diagnostics
• Power down mode
• Auto power down with clock loss detection
• Built in diagnostics
• 850 mW at 60 MHz, 3.3 volts
• 120 pin quad flat pack package
Texas Instruments Incorporated
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This document contains information which may be changed at any time without notice