GC1012B_07 Datasheet, PDF (16/30 Pages) Texas Instruments – 3.3V DIGITAL TUNER CHIP

GC1012B 3.3V DIGITAL TUNER
SLWS138B
3.2 SYNC MODE REGISTER
The sync mode register controls the action of the SS and AS sync strobes and how they affect the
chip’s internal timers, counters, and accumulators.
ADDRESS 4:
Sync Mode Register
BIT
TYPE
NAME
DESCRIPTION
0 (LSB)
R/W
SS_OFF
1
R/W
AS_ON
2
R/W
AS_MUX
3
R/W
LD_FREQ
4
R/W
AS_FREQ
5
R/W
SS_DIAG
6
R/W
7 (MSB)
R/W
TEST
SS_MUX
This bit disables the SS input.
Enables the accumulator sync AS. Normally the frequency accumulator will free
run. This bit causes the frequency accumulator to be initialized to the contents of
the frequency register when AS goes low. SS, instead of AS, will reset the
accumulator if AS_MUX is set and SS is not disabled by SS_OFF.
Use SS for the accumulator sync. The AS input is ignored and the SS strobe is
used in its place when this bit is set and SS is not disabled by SS_OFF. (See
AS_ON and AS_FREQ).
Load the frequency register in the digital oscillator with the contents of the
frequency word registers. If left on, this bit will cause the frequency register to load
whenever a frequency word register is changed.
Enables the synchronous frequency load mode. When this bit is set and AS goes
low, the frequency register will be synchronously loaded with the contents of the
frequency control registers. SS, instead of AS, will load the frequency register if
AS_MUX is set and SS is not disabled by SS_OFF.
Enables diagnostic syncs. This bit routes the internal sync to the checksum
generator and to all accumulators and control counters within the chip. This forces
the chip to re-initialize at the start of every sync period. The internal sync period will
be 2²⁰ clocks if SS_MUX is set, otherwise it will be determined by the period of an
externally provided SS strobe.
Shortens the internal sync counter period from 2²⁰ clocks to 2⁸ clocks. This mode
is used to test chips at the factory.
Use the sync counter’s terminal count strobe for the internal sync instead of the
sync input SS. The internal sync is output on the SO pin.
The operation of these control bits are illustrated in Figure 3.
SS_OFF
SS
CK
TEST
SS_MUX
COUNTER
{ ^{PERIOD =}
2²⁰ IF TEST = 0
2⁸ IF TEST = 1
1
0
SS_DIAG
SYNC TO
CONTROL COUNTERS
AND
OUTPUT CIRCUITS
SYNC TO SO
AS_MUX
AS
AS_ON
AS_FREQ
LD_FREQ
1
0
1
0
Figure 3. Sync Controls
DIAGNOSTIC SYNCS
SYNC FREQ
ACCUMULATOR
LOAD FREQ REGISTER
Texas Instruments Incorporated
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