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GC1012B_07 Datasheet, PDF (19/30 Pages) Texas Instruments – 3.3V DIGITAL TUNER CHIP
GC1012B 3.3V DIGITAL TUNER
SLWS138B
3.5 OUTPUT MODE REGISTER
The output mode register controls the output formatting.
ADDRESS 8:
Output mode register
BIT
TYPE
NAME
DESCRIPTION
0
R/W
IQ_MUX
The IQ_MUX control is used in the complex mode to multiplex the I and Q output
words onto the I[0:15] output pins. Normally the I and Q halves are output on
separate ports. When this bit is high, the halves are multiplexed together so that
the I half is output first, followed by the Q half. The word strobe (WS) rate is doubled
in this mode. The IFLAG output signal is used in this mode to identify the I half of
each complex pair. The Q[0:15] output pins are forced low in this mode.
1
R/W
WS_POL
Changes the polarity of WS.
2
R/W
WS_MODE
Changes the mode of WS. Normally WS pulses high during the clock cycle before
an I or Q output transition. This bit changes WS so that it is a 50% duty cycle clock
with its rising edge in the middle of each output period
3
R/W
-
Unused
4
R/W
R10
Round the output samples to the 10 bits MSBs of the output word.
5
R/W
R12
Round the output samples to the 12 bits MSBs of the output word.
6
R/W
R14
Round the output samples to the 14 bits MSBs of the output word.
7
R/W
R16
Round the output samples to the 16 bits MSBs of the output word.
One and only one of the rounding options should be selected. Unused LSBs are cleared.
The IQ_MUX and WS_MODE controls are illustrated in the timing diagrams shown in Figure 5. Note
that the polarity shown for WS can be changed using the WS_POL control.
DECIMATE BY 2 MODE: (DEC=2)
CK
I or Q
WS
(WS_MODE= 0 or 1)
DECIMATE BY 2 MODE WITH IQ_MUX, OR REAL MODES: (DEC=2, REAL=1 OR IQ_MUX=1)
CK
I
(Q is low, WS is high)
IFLAG
DECIMATE BY 4 MODE: (DEC=3)
CK
I or Q
WS
(WS_MODE= 0)
WS
(WS_MODE= 1)
DECIMATE BY 4 MODE WITH IQ_MUX OR REAL MODES: (DEC=2, REAL=1 OR IQ_MUX=1)
CK
I or Q
WS
(WS_MODE= 0 or 1)
IFLAG
Figure 5. Timing For Output Modes
Texas Instruments Incorporated
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