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CD74HC299 Datasheet, PDF (7/10 Pages) Texas Instruments – High Speed CMOS Logic 8-Bit Universal Shift Register; Three-State
◁
CD74HC299, CD74HCT299
Switching Specifications CL = 50pF, Input tr, tf = 6ns (Continued)
PARAMETER
HCT TYPES
TEST
SYMBOL CONDITIONS VCC (V) MIN
25oC
TYP MAX
-40oC TO
85oC
MIN MAX
-55oC TO
125oC
MIN MAX UNITS
Propagation Delay
Clock to I/O Output,
Clock to Q0 and Q7
tPHL, tPLH
CL = 50pF
4.5
-
-
45
-
56
-
68
ns
CL = 15pF
5
-
19
-
-
-
-
-
ns
MR to Output
tPHL, tPLH CL = 50pF
4.5
-
-
46
-
58
-
69
ns
Output Enable and Disable tPZL, tPZH, CL = 15pF
5
Times
tPLZ, tPHZ
-
10,
-
-
-
-
13, 15
-
ns
Output High-Z to High Level tPZH
CL = 50pF
4.5
-
-
32
-
40
-
48
ns
Output High Level to High-Z tPHZ
CL = 50pF
4.5
-
-
37
-
46
-
56
ns
Output Low Level to High-Z
tPLZ
CL = 50pF
4.5
-
-
32
-
40
-
48
ns
Output High-Z to Low Level
tPZL
CL = 50pF
4.5
-
-
30
-
38
-
45
ns
Output Transition Time
Q0, Q7
tTLH, tTHL
CL = 50pF
4.5
-
-
15
-
19
-
22
ns
I/O0 to I/O7
CL = 50pF
4.5
-
-
12
-
15
-
18
ns
Input Capacitance
CIN
CL = 50pF
-
10
-
10
-
10
-
10
pF
Three-State Output
Capacitance
CO
-
-
20
-
20
-
20
-
20
pF
Power Dissipation Capacitance CPD
CL = 15pF
5
(Notes 4, 5)
- 170 -
-
-
-
-
pF
NOTES:
4. CPD is used to determine the dynamic power consumption, per register.
5. PD = CPD VCC2 fi + ∑ (CL VCC2 fO) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance,
VCC = Supply Voltage.
Test Circuits and Waveforms
trCL
CLOCK
90%
10%
tfCL
50%
10%
tWL
tWL
+
tWH
=
I
fCL
50%
50%
tWH
VCC
GND
trCL = 6ns
CLOCK
2.7V
0.3V
tfCL = 6ns
tWL
+
tWH
=
I
fCL
3V
1.3V
0.3V
1.3V
1.3V
GND
tWL
tWH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
7
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