AM1707 Datasheet, PDF (66/198 Pages) Texas Instruments – AM1707 ARM Microprocessor

AM1707
SPRS637 – FEBRUARY 2010
www.ti.com
A likely use case with more than one EMIFA chip select used for NAND flash is illustrated in Figure 6-13.
This figure shows how two multiplane NAND flash devices with two chip selects each would connect to the
EMIFA. In this case if NAND is the boot memory, then the boot image needs to be stored in the NAND
area selected by EMA_CS[3]. Part of the application image could spill over into the NAND regions
selected by other EMIFA chip selects; but would rely on the code stored in the EMA_CS[3] area to
bootload it.
EMA_CS[0]
EMIFA
EMA_CAS
EMA_RAS
EMA_WE
EMA_CLK
EMA_SDCKE
EMA_BA[1:0]
EMA_A[12:0]
EMA_WE_DQM[0]
EMA_WE_DQM[1]
EMA_D[15:0]
EMA_CS[2]
EMA_CS[3]
EMA_WAIT
EMA_OE
RESET
GPIO
(6 Pins)
RESET
...
CE
CAS
RAS
WE
CLK
CKE
SDRAM
2M x 16 x 4
Bank
BA[1:0]
A[11:0]
LDQM
UDQM
DQ[15:0]
A[0]
A[12:1]
DQ[15:0]
CE
NOR
WE
OE
FLASH
512K x 16
RESET
A[18:13]
RY/BY
D_VDD
EMA_A[1]
ALE
EMA_A[2]
CLE
DQ[15:0]
CE
WE
RE
RB
NAND
FLASH
1Gb x 16
Figure 6-12. Device Connection Diagram: SDRAM, NOR, NAND
66
Peripheral Information and Electrical Specifications
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