AM1707 Datasheet, PDF (104/198 Pages) Texas Instruments – AM1707 ARM Microprocessor

AM1707
SPRS637 – FEBRUARY 2010
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6.17.2.3 Multichannel Audio Serial Port 2 (McASP2) Timing
Table 6-51 and Table 6-52 assume testing over recommended operating conditions (see Figure 6-34 and
Figure 6-35).
Table 6-51. McASP2 Timing Requirements^{(1) (2)}
No.
PARAMETER
1 t_c(AHCLKRX)
Cycle time, AHCLKR2 external, AHCLKR2 input
Cycle time, AHCLKX2 external, AHCLKX2 input
2 t_w(AHCLKRX)
Pulse duration, AHCLKR2 external, AHCLKR2 input
Pulse duration, AHCLKX2 external, AHCLKX2 input
3 t_c(ACLKRX)
Cycle time, ACLKR2 external, ACLKR2 input
Cycle time, ACLKX2 external, ACLKX2 input
4 t_w(ACLKRX)
Pulse duration, ACLKR2 external, ACLKR2 input
Pulse duration, ACLKX2 external, ACLKX2 input
Setup time, AFSR2 input to ACLKR2 internal⁽³⁾
Setup time, AFSX2 input to ACLKX2 internal
Setup time, AFSR2 input to ACLKR2 external input⁽³⁾
5 t_{su(AFSRX-ACLKRX) Setup time, AFSX2 input to ACLKX2 external input}
Setup time, AFSR2 input to ACLKR2 external output⁽³⁾
Setup time, AFSX2 input to ACLKX2 external output
Hold time, AFSR2 input after ACLKR2 internal⁽³⁾
Hold time, AFSX2 input after ACLKX2 internal
Hold time, AFSR2 input after ACLKR2 external input⁽³⁾
6 t_{h(ACLKRX-AFSRX) Hold time, AFSX2 input after ACLKX2 external input}
Hold time, AFSR2 input after ACLKR2 external output⁽³⁾
7
t_{su(AXR-ACLKRX)}
8
t_{h(ACLKRX-AXR)}
Hold time, AFSX2 input after ACLKX2 external output
Setup time, AXR2[n] input to ACLKR2 internal⁽³⁾
Setup time, AXR2[n] input to ACLKX2 internal⁽⁴⁾
Setup time, AXR2[n] input to ACLKR2 external input⁽³⁾
Setup time, AXR2[n] input to ACLKX2 external input⁽⁴⁾
Setup time, AXR2[n] input to ACLKR2 external output⁽³⁾
Setup time, AXR2[n] input to ACLKX2 external output⁽⁴⁾
Hold time, AXR2[n] input after ACLKR2 internal⁽³⁾
Hold time, AXR2[n] input after ACLKX2 internal⁽⁴⁾
Hold time, AXR2[n] input after ACLKR2 external input⁽³⁾
Hold time, AXR2[n] input after ACLKX2 external input⁽⁴⁾
Hold time, AXR2[n] input after ACLKR2 external output⁽³⁾
Hold time, AXR2[n] input after ACLKX2 external output⁽⁴⁾
MIN
13
13
6.5
6.5
greater of 2P or 13
greater of 2P or 13
6.5
6.5
10
10
1.6
1.6
1.6
1.6
-1.9
-2
1.4
1.4
1.4
1.4
10
10
1.6
1.6
1.6
1.6
-2.2
-2.2
1.3
1.3
1.3
1.3
(1) ACLKX2 internal – McASP2 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX2 external input – McASP2 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX2 external output – McASP2 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR2 internal – McASP2 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR2 external input – McASP2 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR2 external output – McASP2 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) P = SYSCLK2 period
(3) McASP2 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR2
(4) McASP2 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX2
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
104 Peripheral Information and Electrical Specifications
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