CC430F613X Datasheet, PDF (62/118 Pages) Texas Instruments – MSP430 SoC with RF Core

CC430F613x
CC430F612x
CC430F513x
ECCN 5E002 TSPA - Technology / Software Publicly Available
SLAS554D – MAY 2009 – REVISED JULY 2010
www.ti.com
USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 19)
f_USCI
PARAMETER
USCI input clock frequency
TEST CONDITIONS
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
V_CC
MIN TYP MAX UNIT
f_SYSTEM MHz
f_SCL
t_HD,STA
t_SU,STA
t_HD,DAT
t_SU,DAT
t_SU,STO
t_SP
SCL clock frequency
Hold time (repeated) START
Setup time for a repeated START
Data hold time
Data setup time
Setup time for STOP
f_SCL ≤ 100 kHz
f_SCL > 100 kHz
f_SCL ≤ 100 kHz
f_SCL > 100 kHz
f_SCL ≤ 100 kHz
f_SCL > 100 kHz
Pulse width of spikes suppressed by input filter
2.2 V/3 V
0
4.0
2.2 V/3 V
0.6
4.7
2.2 V/3 V
0.6
2.2 V/3 V
0
2.2 V/3 V
250
4.0
2.2 V/3 V
0.6
2.2 V
50
3V
50
400 kHz
µs
µs
ns
ns
µs
600
ns
600
SDA
t_HD,STA
t_SU,STA
t_HD,STA
t_BUF
t_LOW
t_HIGH
t_SP
SCL
t_HD,DAT
t_SU,DAT
Figure 19. I2C Mode Timing
t_SU,STO
62
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