TLC320AD77C Datasheet, PDF (6/31 Pages) Texas Instruments – 24-BIT 96 kHz STEREO AUDIO CODEC

3.3.2 ADC Digital Filter, T_A = 25°C, AV_DD = DV_DD = 3.3 V ± 10%,
f_s = 44.1 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
3.3.3 Analog-to-Digital Converter,
T_A = 25°C, AV_DD = DV_DD = 3.3 V, f_s = 44.1 kHz . . . . . . . . . . . . . . . . . . . . 3–2
3.3.4 DAC Interpolation Filter, T_A = 25°C, AV_DD = DV_DD = 3.3 V + 10%,
f_s = 44.1 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
3.3.5 Digital-to-Analog Converter, T_A = 25°C, AV_DD = 3.3 V, f_s = 44.1 kHz,
Input = 1 V_rms Sine Wave at 1 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
3.3.6 Output Performance Data T_A = 25°C, AV_DD = DV_DD = 3.3 V ± 10% . . . . 3–3
3.4 Serial Interface Switching Characteristics,
T_A = 25°C, AV_DD = DV_DD = 3.3 V ± 10% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
3.5 DSP Serial Interface Switching Characteristics,
T_A = 25°C, AV_DD = DV_DD = 3.3 V ± 10% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
4 Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
5.1 Single-Ended to Differential External Analog
Front-End Circuit (f_s = 44.1 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
5.1 External Analog Back-End Circuit (f_s = 44.1 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
Appendix A Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1
List of Illustrations
Figure
Title
Page
2–1 MSB First Right/Left Justified (for 16-, 20-, and 24-bits) . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
2–2 IIS-Compatible Serial Format (for 16-, 20-, and 24-bits) . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
2–3 MSB Left Justified Serial Interface Format (for 16-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
2–4 DSP Compatible Serial Interface Format (for 16-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
2–5 De-Emphasis Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
4–1 Master Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
4–2 Right/Left Justified, IIS, Left/Left Justified Serial Protocol Timing . . . . . . . . . . . . . . . . . 4–1
4–3 DSP Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
4–4 DAC Filter Overall Frequency Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
4–5 DAC Digital Filter Passband Ripple Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
4–6 ADC Digital Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
4–7 ADC Digital Filter Stopband Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
4–8 ADC Digital Filter Passband Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
4–9 ADC High Pass Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
5–1 Analog Front End (right channel) for 0.7 Vrms Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
5–2 Analog Back End (right channel) for 0.7 Vrms Output . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
5–3 Voltage Reference Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
List of Tables
Table
Title
Page
2–1 Example Master Clock Frequency Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
iv