TLC320AD77C Datasheet, PDF (20/31 Pages) Texas Instruments – 24-BIT 96 kHz STEREO AUDIO CODEC

3.4 Serial Interface Switching Characteristics, T_A = 25°C,
AV_DD = DV_DD = 3.3 V ± 10%
PARAMETER
MIN TYP
MAX
f(SCLK)
td(LRCLK)
td(SDOUT)
SCLK frequency
Delay time, LRCLK edge to SCLK rising
Delay time, SDOUT valid from SCLK falling
(see Note 10)
6.144
20
1/(128×fs)
(1/(256×fs))+10
tsu(SDIN)
th(SDIN)
f(LRCLK)
SDIN setup time before SCLK rising edge
SDIN hold time from SCLK rising edge
LRCLK frequency
MCLK duty cycle
20
10
16 44.1
96
50%
SCLK duty cycle
50%
LRCLK duty cycle
50%
NOTE 10: Maximum of 50-pF external load on SDOUT
3.5 DSP Serial Interface Switching Characteristics, T_A = 25°C,
AV_DD = DV_DD = 3.3 V ± 10% (see Note 11)
PARAMETER
MIN TYP
MAX
f(SCLK)
td(FS)
tw(FSHIGH)
td(SDOUT)
SCLK frequency
Delay time, SCLK rising to Fs
Pulse duration, sync
Delay time, SDOUT valid from SCLK rising
(see Note 12)
1/(64×fs)
6.144
25
(1/(256×fs))+10
tsu(SDIN)
SDIN and LRCLK setup time before SCLK falling
edge
20
th(SDIN)
SDIN and LRCLK hold time from SCLK falling edge 10
SCLK duty cycle
50%
NOTES: 11. Burst mode is not supported.
12. Timing parameters for DSP format which samples on the falling edge
UNIT
MHz
ns
ns
ns
ns
kHz
UNIT
MHz
ns
ns
ns
ns
ns
3–4