TLC320AD77C Datasheet, PDF (14/31 Pages) Texas Instruments – 24-BIT 96 kHz STEREO AUDIO CODEC

2.14.2 IIS-Compatible Serial Format
SCLK
LRCLK = fs
SDIN
SDOUT
X MSB
X MSB
LSB
LSB
X MSB
X MSB
LSB
LSB
Left Channel
Right Channel
Figure 2–2. IIS-Compatible Serial Format (for 16-, 20-, and 24-bits)
Note the following characteristics of this protocol.
• Left channel data is valid when LRCLK is low.
• SDIN is sampled with the rising edge of SCLK.
• SDOUT is transmitted on the falling edge of SCLK.
• If LRCLK phase changes by more than 10 MCLKs, then the device is automatically reset.
2.14.3 MSB Left Justified Serial Interface Format
SCLK
LRCLK = fs
SDIN
SDOUT
MSB
MSB
LSB
LSB
MSB
MSB
LSB
LSB
Left Channel
Right Channel
Figure 2–3. MSB Left Justified Serial Interface Format (for 16-bits)
Note the following characteristics of this protocol.
• Left channel data is valid when LRCLK is high.
• The SDIN data is justified to the leading edge of LRCLK.
• The MSBs are valid at the same time as the LRCLK edge for SDOUT, and captured at the very
next rising edge of SCLK for SDIN.
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