TLC320AD77C Datasheet, PDF (16/31 Pages) Texas Instruments – 24-BIT 96 kHz STEREO AUDIO CODEC

2.16.2 Power Down/Reset
The TLC320AD77C is capable of entering a stand-by mode at reduced power when no activity is required.
To initiate the reset sequence, PDN_RSTB is held low for a minimum of 10 ns. As long as the pin is held
low, the device is in the power-down state.
In order for the dynamic logic to be properly powered down, the clocks should not be stopped before the
PDN_RSTB pin goes low. Otherwise, the device may drain additional supply current.
2.16.3 Reinitialization Sequence
When PDN_RSTB is returned to high, the device begins a reinitialization sequence after all clocks are
active. The output data becomes valid after a minimum of 128 LRCLK cycles after the pin is pulled high.
During the initialization sequence the outputs of the DAC and ADC are invalid.
Any change in the control lines (MOD0, MOD1, MOD2, DEM0, DEM1, SPDMOD, PDN_RST) or phase shift
in LRCLK triggers the reinitialization sequence.
In order for the dynamic logic to be properly powered down, the clocks should not be stopped before the
PDN_RSTB pin goes low. Otherwise, the device may drain additional supply current.
2.17 DAC De-Emphasis Filter
De-emphasis is only supported for three sampling rates (f_s): 32 kHz, 44.1 kHz, and 48 kHz in normal speed
operation. The DEM0 and DEM1 pins select the filter coefficients and enable or disable the filter. Figure 2–5
illustrates the de-emphasis filtering characteristics.
0
De-emphasis
–10
3.18
(50 µs)
f – Frequency – kHz
10.6
(15 µs)
Figure 2–5. De-Emphasis Characteristics
2.17.1 De-Emphasis Selection
De-emphasis control is achieved using the DEM1 and DEM0 pins. The pin control is defined in the following
table.
DEM 1
0
0
1
1
DEM 0
0
1
0
1
DE-EMPHASIS
32 kHz
44.1 kHz
48 kHz
Off
2–6