TLC320AD77C Datasheet, PDF (12/31 Pages) Texas Instruments – 24-BIT 96 kHz STEREO AUDIO CODEC

2.7 ADC Analog Input
The ADC accepts a differential input with a maximum value that does not exceed approximately 4 V_pp. See
Section 5.1, Single-Ended to Differential External Analog Front-End Circuit for a description of the
recommended external analog front end.
2.8 DAC Analog Output
The DAC outputs a single-ended signal with a max value of 0.7 Vrms. See Section 5.2, External Analog
Back-End Circuit for a description of the recommended back-end circuit.
2.9 Sigma-Delta ADC
The sigma-delta ADC is a third order modulator with 128 times oversampling in normal speed operation.
The ADC provides high resolution and low noise performance using over-sampling techniques.
2.10 Decimation Filter
The decimation filter reduces the digital data rate to the sampling rate. This is accomplished by decimating
with a ratio of 1:128. The output of this filter is a 2s complement 16-, 20-, 24-bit word clocking at the sample
rate selected.
2.11 Sigma-Delta DAC
The sigma-delta DAC is a seventh order modulator with 128 times oversampling. The DAC provides
high-resolution, low noise, from a 1-bit converter using over-sampling techniques.
2.12 Interpolation Filter
The interpolation filter resamples the digital data at a rate 128 times the incoming sample rate. The
high-speed data output is then used in the sigma-delta DAC.
2.13 De-emphasis
De-emphasis is supported for three sampling rates: 32 kHz, 44.1 kHz, and 48 kHz and selected with the
DEM0 and DEM1 pins.
2.14 Serial Interface Formats
The TLC320AD77C operates only in slave mode. It requires externally supplied MCLK (master clock), and
LRCLK (left/right clock), and SCLK (shift clock) inputs. There are two options for selecting the clock rates.
If a 384 f_s MCLK rate is selected, then a LRCLK frame of 48 SCLKs must be supplied. If a 256 f_s MCLK is
selected, then a LRCLK of 64 SCLKs must be supplied.
• A detection circuit automatically senses at which rate the MCLK is operating.
• The MCLK and SCLK must be synchronous and their edges must be at least 3 ns apart.
• If the LRCLK phase changes more than 10 MCLKs then the device automatically resets.
The TLC320AD77C is compatible with eight different serial interfaces. Available interface options are IIS,
right justified, left justified, and DSP frame. The following table indicates how the eight options are selected
using the MOD0, MOD1, and MOD2 pins. All serial interface options at either 16-, 20-, or 24-bits can operate
with SCLK at 48*f_s or 64*f_s except for the 16-bit DSP mode which should use SCLK = 64 f_s.
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