THS1031 Datasheet, PDF (6/26 Pages) Texas Instruments – 2.7 V . 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER

THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
electrical characteristics, AV_DD = 3 V, DV_DD = 3 V, Fs = 30 MSPS/50% duty cycle, MODE = AV_DD, 2 V
input span from 0.5 V to 2.5 V, external reference, PGA = 1X, T_A = –40°C to 85°C (unless otherwise
noted) (continued)
dynamic performance (ADC and PGA)
PARAMETER
ENOB Effective number of bits
SFDR Spurious free dynamic range
THD Total harmonic distortion
SNR Signal-to-noise
SINAD Signal-to-noise and distortion
PGA
Gain range (linear scale)
Gain step size (linear scale)
Gain error from nominal
Number of control bits
clamp DAC
Resolution
DAC output range
Clamping analog output voltage range
Clamping analog output voltage error
PARAMETER
PARAMETER
TEST CONDITIONS
f = 3.5 MHz
f = 3.5 MHz, AVDD = 5 V
f = 15 MHz
f = 15 MHz, AVDD = 5 V
f = 3.5 MHz
f = 3.5 MHz, AVDD = 5 V
f = 15 MHz
f = 15 MHz, AVDD = 5 V
f = 3.5 MHz
f = 3.5 MHz, AVDD = 5 V
f = 15 MHz
f = 15 MHz, AVDD = 5 V
f = 3.5 MHz
f = 3.5 MHz, AVDD = 5 V
f = 15 MHz
f = 15 MHz, AVDD = 5 V
f = 3.5 MHz
f = 3.5 MHz, AVDD = 5 V
f = 15 MHz
f = 15 MHz, AVDD = 5 V
MIN TYP MAX
8.2
9
8.8
7.7
7.64
55
60
63
48
52.4
– 58.2 – 54.7
– 68.7
– 47
– 51.9
51.2
56
55
53
49.3
51.1
56
55
48.1
47.7
UNIT
Bits
dB
dB
dB
dB
MIN TYP MAX UNIT
0.5
4 V/V
0.5
3%
3
Bits
MIN
REFBF
0.1
– 40
TYP MAX
10
REFTF
AVDD– 0.1
+ 40
UNIT
Bits
V
mV
6
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