THS1031 Datasheet, PDF (19/26 Pages) Texas Instruments – 2.7 V . 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER

THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
PRINCIPLES OF OPERATION
analog input mode(continued)
differential input
In this mode, the first differential input is applied to the AIN pin and the second differential input is applied to the
common point where REFTS and REFBS are tied together. The common mode of the input should be set to
AV_DD/2 as shown in Figure 20. The maximum magnitude of the differential input signal should be equal to V_REF.
VREF
THS1031
AIN
AVDD/2
REFTS
SHA
PGA
A/D
REFBS
AVDD ^MODE
VREF
VREF is either internal or external
ADC
REF
REFTF
0.1 µF
REFBF
0.1 µF
10 µF
0.1 µF
Figure 20. Differential Input
digital input mode
The THS1031 contains 4 registers: two CLAMP registers, a CONTROL register, and a TEST register. The TEST
register is reserved for test purposes. Binary data can be written into the CLAMP and CONTROL registers via
I/O0– I/O9 by inserting an active-low write strobe to the WR input pin and an active-low signal to the OE input
pin. This will disable the ADC’s output bus. The two MSBs of each register are address bits. For example, set
bit 9 and bit 8 to 00 to select the clamp register 1. Set bit 9 and bit 8 to 01 to select the clamp register 2.
clamp registers
The internal digital clamp circuit uses a 10-bit DAC to convert the 10-bit digital value into the analog clamp level
in which the clamp register 1 contains 8 LSBs of DAC(7:0). The clamp register 2 contains two MSBs of the
DAC(9:8). DAC(9:8) (Default = 00): For clamping purpose, the entire range of voltage reference V_REF is divided
into 4 quarters which can be selected by bit 0 (DAC8) and bit 1 (DAC9) in the clamp register 2. The user can
clamp to any of 256-dc levels within each quarter determined by the 8-bit content of the clamp register 1.
Figure 21 shows how the DACs 10-bit digital input map to the analog clamping range from 0 V to V_REF.
D Clamp Register 1
9
8
7
6
5
4
3
2
1
0
0
0
DAC7
DAC6
DAC5
DAC4
DAC3
DAC2
DAC1
DAC0
D Clamp Register 2
9
8
7
6
5
4
3
2
1
0
0
1
X
X
X
X
X
X
DAC9
DAC8
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