THS1031 Datasheet, PDF (23/26 Pages) Texas Instruments – 2.7 V . 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER

THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
PRINCIPLES OF OPERATION
clamp operation (continued)
requirements
For a single direct source of NTSC video,
D The initial clamp acquisition time needs to be between 130 µs and 160 µs to set the input dc level within
1 mV accuracy.
D The clamp pulse at CLAMP is recommended to be 2 µs (typ).
D The droop voltage needs to be compensated within one clamping period of 64 µs for 1 V and 2 V. Input
ranges are 1 mV and 1.9 mV respectively which are less than 1 LSB.
power management
Upon power up, the THS1031 is put in the default mode. In the default mode, the PGA (PGA bypass) and the
clamp DAC are powered down which adds to the device’s flexibility. The users need not incur the penalty of
having to provide power for a certain section if it is not necessary to their design.
When bit 3 of PGA/control register is set to 1, the entire device is powered down. The ADC will wake-up in 400 ns
(typ) after the bit 3 is reset.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
23