THS1031 Datasheet, PDF (21/26 Pages) Texas Instruments – 2.7 V . 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER

THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
PRINCIPLES OF OPERATION
digital input mode (continued)
D PGA(2–0): (Default = 001) 3-bit gain for programmable gain amplifier can be set as indicated in the following
table:
PGA[2– 0]
000
001
010
011
100
101
110
111
GAIN
0.5
Unity gain
1.5
2.0
2.5
3.0
3.5
4.0
test register (reserved)
9
8
7
6
5
4
3
2
1
0
1
1
X
X
X
X
X
X
X
X
digital output mode
D 3-State Output: The digital outputs can be set to high-impedance state by applying a Hi logic to the OE
pin.
D Output Format: Defined by bit 5 of the CONTROL register. The output format is straight binary if bit 5 set
to 0. The output format is 2s complement if bit 5 is set to 1. The default format is straight binary.
clamp operation
The THS1031 ADC features an internal clamp circuit for dc restoration of video or ac coupled signals. The clamp
input level can come from either an external source or an internal digital clamp circuit containing a 10-bit DAC
and clamp register.
D External Clamp Input: To enable the external clamp input source, use the default state on power up or
write a 0 to bit 4 of the PGA/CONTROL register. This will connect the switch SW2 to the CLAMPIN pin. The
clamp amplifier will then servo the voltage at the AIN pin to be equal to the clamp voltage applied at the
CLAMPIN pin. After the desired clamp level is attained, the switch SW1 is opened by taking CLAMP back
to logic low. Ignoring the droop caused by the input bias current, the input capacitor CIN will hold the DC
voltage at AIN constant until the next clamp interval. The input resistor RIN has a minimum recommended
value of 10 W, to maintain the closed-loop stability of the clamp amplifier.
D Internal Programmable Digital Clamp Input: The THS1031 ADC features a programmable digital clamp
circuit to set more precise clamping level to 1-LSB accuracy for dc restoration of video or ac coupled signals.
Figure 22 shows the internal clamp circuitry and the external control signals needed for the digital clamp
operation. To enable the digital clamp input source, write a 1 to bit 4 of the CONTROL register which will
connect the switch SW2 to the output of the 10-bit clamp DAC. In the CLAMP register, bit 0 to bit 7 are used
to set the clamp level input to the 10-bit DAC and bit 6–7 are used to select one of 4 equal clamping voltage
sub-ranges as described in the description of CLAMP REGISTER for digital input mode. The clamp
amplifier will then servo the voltage at the AIN pin to be equal to the clamp voltage applied at the CLAMPIN
pin. After the desired clamp level is attained, the switch SW1 is opened by taking CLAMP back to logic low.
Ignoring the droop caused by the input bias current, the input capacitor CIN will hold the dc voltage at AIN
constant until the next clamp interval. The input resistor RIN has a minimum recommended value of 10 W,
to maintain the closed-loop stability of the clamp amplifier.
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