THS1031 Datasheet, PDF (20/26 Pages) Texas Instruments – 2.7 V . 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER

THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
PRINCIPLES OF OPERATION
digital input mode (continued)
REFTF _{DAC (9:0)}
1111111111
•
•
•
3/4 (REFTF – REFBF)
1100000000
1011111111
•
•
•
1/2 (REFTF – REFBF)
1000000000
0111111111
•
•
•
1/4 (REFTF – REFBF)
0100000000
0011111111
•
•
•
0000000000
REFBF
Figure 21. Digital Clamp Input Range
control register
9
8
7
1
0
X
6
Clamp Disable
5
Bin/2’s Output
4
INT/EXT Clamp
3
Power Down
2
PGA2
1
PGA1
0
PGA0
D Clamp Disable: (Default = 0) Set bit 6 to 1 to disable the internal clamp amplifier for power savings.
D BIN/2s Output: (Default is straight binary) Set bit 5 to 0 to set the output data format to straight binary or
set bit 5 to1 to set the output data format to 2s complement.
D INT/EXT Clamp: (Default = 0) Set bit 4 of the CONTROL register to 0 to select the external analog clamp
or set bit 4 to 1 to select the internal digital clamp whose clamp level is defined in the clamp register
described above.
D Power Down: (Default = 0) Set bit 3 of the CONTROL register to 1 to power down the THS1031.
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