SN74AUP1G74 Datasheet, PDF (6/17 Pages) Texas Instruments – LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

SN74AUP1G74
LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES644A – MARCH 2006 – REVISED SEPTEMBER 2006
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
f_clock
Clock frequency
t_w
Pulse duration
CLK high or low
PRE or CLR low
Data high
t_su
Setup time before CLK↑ Data low
PRE or CLR inactive
t_h
Hold time, data after CLK↑
V_CC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
T_A = 25°C
TYP
21
3.5
4.5
3
1
1
0
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T_A = –40°C to
85°C
MIN MAX
UNIT
40
50
MHz
60
90
90
2
2
2
2
2
ns
2
2
2
2
2
1.3
1
1
0.5
0.5
1.2
1
ns
1
1
1
0.5
0.5
0.5
0.5
0.5
0
0
ns
0
0
0
6
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