SN74AUP1G74 Datasheet, PDF (4/17 Pages) Texas Instruments – LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

SN74AUP1G74
LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES644A – MARCH 2006 – REVISED SEPTEMBER 2006
Recommended Operating Conditions⁽¹⁾
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V_CC
Supply voltage
V_IH
High-level input voltage
V_IL
Low-level input voltage
V_I
Input voltage
V_O
Output voltage
I_OH
High-level output current
I_OL
Low-level output current
∆t/∆v
T_A
Input transition rise or fall rate
Operating free-air temperature
V_CC = 0.8 V
V_CC = 1.1 V to 1.95 V
V_CC = 2.3 V to 2.7 V
V_CC = 3 V to 3.6 V
V_CC = 0.8 V
V_CC = 1.1 V to 1.95 V
V_CC = 2.3 V to 2.7 V
V_CC = 3 V to 3.6 V
V_CC = 0.8 V
V_CC = 1.1 V
V_CC = 1.4 V
V_CC = 1.65
V_CC = 2.3 V
V_CC = 3 V
V_CC = 0.8 V
V_CC = 1.1 V
V_CC = 1.4 V
V_CC = 1.65 V
V_CC = 2.3 V
V_CC = 3 V
V_CC = 0.8 V to 3.6 V
MIN
0.8
V_CC
0.65 × V_CC
1.6
2
0
0
–40
MAX
3.6
0
0.35 × V_CC
0.7
0.9
3.6
V_CC
–20
–1.1
–1.7
–1.9
–3.1
–4
20
1.1
1.7
1.9
3.1
4
200
85
UNIT
V
V
V
V
V
µA
mA
µA
mA
ns/V
°C
(1) All unused inputs of the device must be held at V_CC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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