SN74AUP1G74 Datasheet, PDF (3/17 Pages) Texas Instruments – LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

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CLR ⁶
CLK ¹
D2
SN74AUP1G74
LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES644A – MARCH 2006 – REVISED SEPTEMBER 2006
LOGIC DIAGRAM (POSITIVE LOGIC)
C
C
C
C
TG
TG
C
TG
C
C
TG
3
Q
5Q
C
C
C
PRE ⁷
Absolute Maximum Ratings⁽¹⁾
over operating free-air temperature range (unless otherwise noted)
V_CC
Supply voltage range
V_I
Input voltage range⁽²⁾
V_O
Voltage range applied to any output in the high-impedance or power-off state⁽²⁾
V_O
Output voltage range in the high or low state⁽²⁾
I_IK
Input clamp current
V_I < 0
I_OK
Output clamp current
V_O < 0
I_O
Continuous output current
Continuous current through V_CC or GND
DCT package
θ_JA
Package thermal impedance⁽³⁾
DCU package
YEP/YZP package
T_stg
Storage temperature range
MIN
MAX UNIT
–0.5
4.6 V
–0.5
4.6 V
–0.5
4.6 V
–0.5 V_CC + 0.5
V
–50 mA
–50 mA
±20 mA
±50 mA
220
227 °C/W
102
–65
150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
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