SLK2511 Datasheet, PDF (6/21 Pages) Texas Instruments – OC-48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER

SLK2511
OC-48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER
SLLS522A – JUNE 2002 – REVISED OCTOBER 2002
Terminal Functions(Continued)
control/status pins (continued)
TERMINAL
NAME
NO.
PAR_VALID
2
PRBSPASS
42
REFCLKSEL
40
SPILL
49
TYPE
TTL output
TTL output
TTL input (with pulldown)
TTL output
DESCRIPTION
Parity checker output. The internal parity checker on the parallel side of the transmitter
checks for even parity. If there is a parity error, the pin is pulsed low for 2 clock cycles.
PRBS test result. This pin reports the status of the PRBS test results (high = pass).
When PRBSEN is disabled, the PRBSPASS pin is set low. When PRBSEN is enabled
and a valid PRBS is received, then the PRBSPASS pin is set high.
Reference clock select. The device can accept a clock frequency of 155.52 MHz or
622.08 MHz, which is selected by this pin (0 = 622.08-MHz mode and 1 = 155.52-MHz
mode).
TX FIFO collision output
voltage supply and reserved pins
TERMINAL
NAME
GND
NO.
1, 6, 19, 23, 26,
28, 30, 31, 33
GNDA
10, 13
GNDLVDS 61, 69, 76, 77,
89, 93, 96, 100
GNDPLL
12
RSVD
52
VDD
3, 22, 25, 29,
32, 35, 50
VDDA
7, 16
VDDLVDS
62, 72, 75, 78,
90, 91, 92, 97
VDDPLL
11
TYPE
Ground
Ground
Ground
Supply
Reserved
Supply
Supply
Supply
Supply
Digital logic ground
DESCRIPTION
Analog ground
LVDS ground
PLL ground
This pin needs to be tied to ground or left floating for normal operation.
Digital logic supply voltage (2.5 V)
Analog voltage supply (2.5 V)
LVDS supply voltage (2.5 V)
PLL voltage supply (2.5 V)
6
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