SLK2511 Datasheet, PDF (5/21 Pages) Texas Instruments – OC-48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER

SLK2511
OC-48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER
SLLS522A – JUNE 2002 – REVISED OCTOBER 2002
Terminal Functions(Continued)
control/status pins
TERMINAL
NAME
NO.
AUTO_DETECT 34
CONFIG0,
17
CONFIG1
18
ENABLE
44
FRAME_EN
27
LCKREFN
24
LLOOP
53
LOL
45
LOOPTIME
51
LOS
46
PRBSEN
41
PRE1,
4
PRE2
5
PS
21
RATEOUT0,
37
RATEOUT1
36
RESET
48
RLOOP
54
RSEL0, RSEL1
39
38
RX_MONITOR
47
SIGDET
20
TESTEN
43
TYPE
TTL input (with pulldown)
TTL input (with pulldown)
TTL input (with pullup)
TTL input (with pullup)
TTL input (with pullup)
TTL input (with pulldown)
TTL output
TTL input (with pulldown)
TTL output
TTL input (with pulldown)
TTL input (with pulldown)
TTL input (with pulldown)
TTL output
TTL input
TTL input (with pulldown)
TTL input (with pulldown)
TTL input (with pulldown)
TTL input (with pulldown)
TTL input (with pulldown)
DESCRIPTION
Data rate autodetect enable. Enable the autodetection function for different data rates.
Configuration pins. Put the device under one of the four operation modes: TX only, RX
only, transceiver, or repeater mode.
Standby enable. When this pin is held low, the device is disabled for IDDQ testing.
When high, the device operates normally.
Frame sync enable. When this pin is asserted high, the frame synchronization circuit
for byte alignment is turned on.
Lock to reference. When low, RXCLKP/N output is forced to lock to REFCLK. When
high, RXCLKP/N is the divided down clock extracted from the receive serial data.
Local loopback enable. When high, the serial output is internally looped back to its
serial input.
Loss of lock. When the clock recovery loop has locked to the input data stream and the
phase differs by less than 100 ppm from REFCLK then LOL is high. When the phase of
the input data stream differs by more than 100 ppm from REFCLK, then LOL is low. If
the difference is too big (> 500 ppm), the LOL output is not valid.
Loop timing mode. When high, the PLL for clock synthesizer is bypassed. The
recovered clock timing is used to send the transmit data.
Loss of signal. When no transitions appear on the input data stream for more than
2.3 µs, a loss of signal occurs and LOS goes high. The device also transmits all zeroes
downstream using REFCLK as its clock source. When a valid SONET signal is
received the LOS signal goes low.
PRBS testing enable. When this pin is asserted high, the device is put into the PRBS
testing mode.
Programmable de-emphasis control. Combinations of these two bits can be used to
optimize serial data transmission.
Polarity select. This pin, used with the SIGDET pin, sets the polarity of SIGDET. When
high, SIGDET is an active low signal. When low, SIGDET is an active high signal.
Autorate detection outputs. When AUTO_DETECT is high, the autodetection circuit
generates these two bits to indicate the data rates for the downstream device.
TXFIFO and LOL reset pin. Low is reset and high is normal operation.
Remote loopback enable. When high, the serial input is internally looped back to its
serial output with the timing extracted from the serial data.
Data rate configuration pins. Puts the device under one of the four data rate operations:
OC-48, OC-24, OC-12, or OC-3.
RX parallel data monitor in repeater mode. This pin is only used when the device is put
under the repeater mode. When high, the RX demux circuit is enabled and the parallel
data is presented. When low, the demux is shut down to save power.
Signal detect. This pin is generally connected to the output of an optical receiver. This
signal may be active high or active low depending on the optical receiver. The SIGDET
input is XORed with the PS pin to select the active state. When SIGDET is in the
inactive state, data is processed normally. When activated, indicating a loss of signal
event, the transmitter transmits all zeroes and force the LOS signal to go high.
Production test mode enable. This pin should be left unconnected or tied low.
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