DS92001 Datasheet, PDF (6/17 Pages) National Semiconductor (TI) – 3.3V B/LVDS-BLVDS Buffer

DS92001
SNLS147F – JUNE 2002 – REVISED APRIL 2013
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Figure 8. TRI-STATE Delay Test Circuit
Figure 9. Output active to TRI-STATE and TRI-STATE to active output time
Pin Name
GND
IN −
IN+
N/C
V_CC
OUT+
OUT -
EN
GND
Pin #
1
2
3
4
5
6
7
8
DAP
PIN DESCRIPTIONS
Input/Outp
ut
Description
P
Ground
I
Inverting receiver B/LVDS input pin
I
Non-inverting receiver B/LVDS input pin
NA
"NO CONNECT" pin
P
Power Supply, 3.3V ± 0.3V.
O
Non-inverting driver BLVDS output pin
O
Inverting driver BLVDS output pin
I
Enable pin. When EN is LOW, the driver is disabled and the BLVDS outputs
are in TRI-STATE. When EN is HIGH, the driver is enabled. LVCMOS/LVTTL
levels.
P
WSON Package Ground
6
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