DS92001 Datasheet, PDF (4/17 Pages) National Semiconductor (TI) – 3.3V B/LVDS-BLVDS Buffer

DS92001
SNLS147F – JUNE 2002 – REVISED APRIL 2013
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.⁽¹⁾
Symbol
Parameter
Conditions
LVDS OUTPUT AC SPECIFICATIONS (OUT)
t_PHLD
t_PLHD
Differential Propagation Delay High
to Low⁽²⁾
Differential Propagation Delay Low
to High⁽²⁾
V_ID = 200mV, V_CM = 1.2V,
R_L = 27Ω or 50Ω, C_L = 15pF
See Figure 5 and Figure 6
t_SKD1
t_SKD3
t_SKD4
t_LHT
t_HLT
Pulse Skew |t_PLHD − t_PHLD|
(measure of duty cycle)⁽³⁾⁽⁴⁾
Part-to-Part Skew⁽³⁾⁽⁵⁾
Part-to-Part Skew⁽³⁾⁽⁶⁾
Rise Time⁽³⁾⁽²⁾
20% to 80% points
Fall Time⁽³⁾⁽²⁾
80% to 20% points
R_L = 50Ω or 27Ω, C_L = 15pF
See Figure 5 and Figure 7
t_PHZ
Disable Time (Active High to Z)
R_L = 50Ω, C_L = 15pF See Figure 8 and Figure 9
t_PLZ
Disable Time (Active Low to Z)
t_PZH
Enable Time (Z to Active High)
t_PZL
Enable Time (Z to Active Low)
t_DJ
LVDS Data Jitter, Deterministic
V_ID = 300mV; PRBS = 2²³ − 1 data; V_CM = 1.2V at
(Peak-to-Peak) ⁽⁷⁾
400Mbps (NRZ)
t_RJ
LVDS Clock Jitter, Random⁽⁷⁾
V_ID = 300mV; V_CM = 1.2V at 200MHz clock
f_MAX
Maximum specified frequency⁽⁸⁾
V_ID = 200mV, V_CM = 1.2V
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Min Typ Max Units
1.0
1.4
2.0
ns
1.0
1.4
2.0
ns
0
20 200 ps
0
200 300 ps
0
1
ns
0.350 0.6
1.0
ns
0.350 0.6
1.0
ns
3
25
ns
3
25
ns
100 120 ns
100 120 ns
78
ps
36
ps
200 300
MHz
(1) All typical are given for V_CC = +3.3V and T_A = +25°C, unless otherwise stated.
(2) Propagation delay, rise and fall times are specified by design and characterization to 200MHz. Generator for these tests: 50MHz ≤ f ≤
200MHz, Zo = 50Ω, tr, tf ≤ 0.5ns. Generator used was HP8130A (300MHz capability).
(3) The parameters are specified by design. The limits are based on statistical analysis of the device performance over the PVT (process,
voltage and temperature) range.
(4) t_SKD1, |t_PLHD − t_PHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel (a measure of duty cycle).
(5) t_SKD3, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This
specification applies to devices at the same V_CC and within 5°C of each other within the operating temperature range. This parameter
specified by design and characterization.
(6) t_SKD4, Part to Part Skew, is the differential channel-to- channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. t_SKD4 is defined as |Max − Min|
differential propagation delay.
(7) The parameters are specified by design. The limits are based on statistical analysis of the device performance over the PVT range with
the following test equipment setup: Agilent 86130A used as stimulus, 5 feet of RG142B cable with DUT test board and Agilent 86100A
(digital scope mainframe) with Agilent 86122A (20GHz scope module). Data input jitter pk to pk = 22 picoseconds; Clock input jitter = 24
picoseconds; t_DJ measured 100 picoseconds, t_RJ measured 60 picoseconds.
(8) f_MAX test: Generator (HP8133A or equivalent), Input duty cycle = 50%. Output criteria: VOD ≥ 200mV, Duty Cycle better than 45/55%.
This specification is specified by design and characterization. A minimum is specified, which means that the device will operate to
specified conditions from DC to the minimum specified AC frequency. The typical value is always greater than the minimum
specification.
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