CDC5806 Datasheet, PDF (6/8 Pages) Texas Instruments – THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS

CDC5806
SCAS760A – MARCH 2004 – REVISED JULY 2004
V_DD
R = 1 kΩ
From Output
of DUT
R = 1 kΩ
C_L = 10 pF
f_AUDCLK
/MHz
Figure 1. LVCMOS Output Test Load
t_L Lock-Up Time
f_target
< 1%
t_L(ω)
Lock Time
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f_target
< 1%
V_DD
/V
f_{REF_IN}
/MHz
V_PUC
f = 54 MHz
AUDSEL
/V
Time/ms
Time/ms
Time/ms
Figure 2. Timing Diagram of PLL Lock Time of Audio Clock
Time/ms
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