CDC5806 Datasheet, PDF (4/8 Pages) Texas Instruments – THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS

CDC5806
SCAS760A – MARCH 2004 – REVISED JULY 2004
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted)⁽¹⁾
Supply voltage range, V_DD
Input voltage range, V_I(2)
Output voltage range, V_O(2)
Input current (V_I < 0, V_I>V_DD)
Continuous output current, I_O
Package thermal impedance,Θ_JA(3): TSSOP20 package
Storage temperature range T_stg
0.5 V to 4.6 V
0.5 V to VDD + 0.5 V
0.5 V to VDD + 0.5 V
±20 mA
±50 mA
104 C/W
65°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51 (no airflow condition) and JEDEC2S1P (high-k board).
RECOMMENDED OPERATING CONDITIONS
V_DD
T_A
V_IL
V_{I thresh}
V_IH
V_IL(L)
V_IM(M)
V_IH(H)
I_OH
I_OL
V_I
C_L
Supply voltage
Operating free-air temperature
Low-level input voltage REF_IN
Input voltage threshold REF_IN
High-level input voltage REF_IN
Three level input low for control inputs
Three level input mid for control inputs
Three level input high for control inputs
High-level output current LVCMOS
Low-level output current LVCMOS
Input voltage range LVCMOS
Output load LVCMOS
MIN NOM
3
3.3
-40
0.5 V_DD
0.7 V_DD
0.4 V_DD
0.87 V_DD
0
5
MAX
3.6
85
0.3 V_DD
0.13 V_DD
0.6 V_DD
-8
8
3.6
10
UNIT
V
°C
V
V
V
V
V
V
mA
mA
V
pF
TIMING REQUIREMENTS
over recommended ranges of supply voltage, load, and operating free-air temperature
PARAMETER
REF_IN REQUIREMENTS
f_{CLK_IN} LVCMOS REF_IN clock input frequency
t_r / t_f
Rise and fall time REF_IN signal (20% to 80%)
duty_REF Duty cycle of REF_IN (VDD/2)
AUDSEL, VIDSEL, MCSEL REQUIREMENTS
t_r / t_f
Rise and fall time (20% to 80%)
t₁
Transitional time between AUDSEL and VIDSEL control pins⁽¹⁾
MIN NOM MAX UNIT
40%
54
MHz
4
ns
60%
4
ns
6
ns
(1) If VIDSEL and AUDSEL are switched from from one state to another state at the same time, then the CPUCLK, ASICCLK, USBCLK, or
MCCLK are affected. This is due to the selected reserved mode with VIDSEL = M and AUDSEL = M. This mode causes the PLL3 to be
bypassed and the REFCLK will be seen with the appropriate divider ratios at the correspondent outputs.
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