CDC5806 Datasheet, PDF (5/8 Pages) Texas Instruments – THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS

CDC5806
www.ti.com
SCAS760A – MARCH 2004 – REVISED JULY 2004
DEVICE CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
OVERALL
I_CC Supply current
I_CC(ST) Standby current
V_PUC Supply voltage threshold for power up control circuit
LVCMOS
Test load
f_IN = 0 MHz, V_DD = 3.6 V
V_IK LVCMOS input voltage
I_I
REF_IN input current
I_I
SELECT input current
V_OH High-level output voltage
V_OL Low-level output voltage
I_OH High-level output current
I_OL
Low-level output current
AC
V_DD = 3 V, I_I = –18 mA
V_I = 0 V or V_DD
V_I = 0 V or V_DD
V_DD = MIN to MAX, I_OH = –5 mA
V_DD = MIN to MAX, I_OL= 5 mA
V_DD = 3 V, V_O = V_DD – 0.4 V
V_DD = 3.3 V, V_O = 1.65 V
V_DD = 3.6 V, V_O = 0.4 V
V_DD = 3 V, V_O = 0.4 V
V_DD = 3.3 V, V_O = 1.65 V
V_DD = 3.6 V, V_O = V_DD – 0.4V
C_I
Input capacitance (Ref_IN)
f_err
Output accuracy VIDCLK, CPUCLK, ASICCLK,
USBCLK, MCCLK (38.4 MHz, 19.2 MHz, 12 MHz)
See Note ⁽¹⁾
f_err
Output accuracy AUDCLK (16.9344 MHz, 12.288 MHz) See Note ⁽¹⁾
t_L
PLL start up lock time
See Figure 2
t_L(ω) PLL lock time after frequency change on AUDCLK
See Figure 2
odc Duty cycle for MCCLK
Threshold = VDD/2
odc
Duty cycle for VIDCLK, AUDCLK, CPUCLK, ASICCLK,
USBCLK
Threshold = VDD/2
t_r/t_f
Rise and fall time of the output
VIDCLK
(74.175824 MHz)
20%–80% of V_O
CPUCLK (64 MHz)
USBCLK (48 MHz)
t_jit(per) Peak-to-peak period jitter for
MCCLK (38.4 MHz)
ASICCLK (32 MHz)
10,000 cycles
MCCLK (19.2 MHz)
AUDCLK (16.9344 MHz)
AUDCLK (12.288 MHz)
MCCLK (12 MHz)
MIN TYP MAX UNIT
35
45 mA
1.1 mA
2
V
V_DD – 0.4
–5
5
–1.2 V
±5 µA
±55 µA
V
0.4 V
–35
mA
–75
35
mA
75
47%
45%
2
50%
50%
75
60
65
65
60
70
75
85
65
pF
±1 ppm
±40 ppm
0.5 ms
0.5 ms
53%
55%
2 ns
150
150
150
150
150 ^ps
150
150
150
150
(1) This parameter is assured by design as a result of the chosen settings of the internal dividers in the PLL's.
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