CDC5806 Datasheet, PDF (2/8 Pages) Texas Instruments – THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS

CDC5806
SCAS760A – MARCH 2004 – REVISED JULY 2004
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
PLL1VDD
PLL2VDD
PLL3VDD
VIDSEL
100 kΩ
100 kΩ
REF_IN
AUDSEL
100 kΩ
100 kΩ
PLL3VDD
Power
Down
Logic
MCSEL
100 kΩ
100 kΩ
PLL 1
74.175824 MHz
PLL 2
12.288/16.9344 MHz
PLL 3
192 MHz
MUX
LVCMOS
VIDCLK
LVCMOS
AUDCLK
CPUCLK
/3
LVCMOS
ASICCLK
/6
LVCMOS
USBCLK
/4
LVCMOS
/5
MCCLK
LVCMOS
/10
MUX
/16
PLL1VSS
PLL2VSS
PLL3VSS
2