CDC5806 Datasheet, PDF (3/8 Pages) Texas Instruments – THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS

CDC5806
www.ti.com
SCAS760A – MARCH 2004 – REVISED JULY 2004
Terminal Functions
TERMINAL
NAME
NO
REF_IN
2
VIDSEL
1
AUDSEL
9
MCSEL
10
VIDCLK
AUDCLK
CPUCLK
ASICCLK
USBCLK
MCCLK
VDD_PLL1
VDD_PLL2
VDD_PLL3
VSS_PLL1
VSS_PLL2
VSS_PLL3
4
7
17
20
14
4
3
6
13, 16, 19
5
8
12, 15, 18
TYPE DESCRIPTION
I LVCMOS Reference frequency input
I LVCMOS VIDSEL select input for VIDCLK. It selects between 74.175824 MHz from PLL1 and buffered
input frequency of 54 MHz, 100k||100k pull to mid-level.
I LVCMOS AUDSEL select input for AUDCLK. It selects between 16.9344 MHz and 12.288 MHz from
PLL2, 100k||100k pull to mid level.
I LVCMOS MCSEL select input for MCCLK. It selects from 38.4 MHz, 19.2 MHz, and 12 MHz from PLL3,
100k||100k pull to mid level.
O LVCMOS VIDCLK output 74.175824 MHz or 54 MHz
O LVCMOS AUDCLK output 16.9344 MHz or 12.288 MHz
O LVCMOS CPUCLK output 64 MHz
O LVCMOS ASICCLK output 32 MHz
O LVCMOS USBCLK output 48 MHz
O LVCMOS MCCLK output 38.4 MHz / 19.2 MHz / 12 MHz
Power
3.3-V supply for PLL1 and VIDCLK
Power
3.3-V supply for PLL2 and AUDCLK
Power
3.3-V supply for PLL3 and CPUCLK, ASICCLK, USBCLK, and MCCLK
Ground
Ground for PLL1 and VIDCLK
Ground
Ground for PLL2 and AUDCLK
Ground
Ground for PLL3 and CPUCLK, ASICCLK, USBCLK, and MCCLK
FUNCTIONAL DESCRIPTION OF THE LOGIC
Table 1. Select Function for Video, Audio, CPU, ASIC, and USB Clocks
VIDSEL
L
L
L
M
M
M
H
H
H
AUDSEL
L
M
H
L
M
H
L
M
H
VIDCLK
54 (buffered)
Reserved
54 (buffered)
Reserved
Reserved
Reserved
74.175824
Reserved
74.175824
AUDCLK
12.288
Reserved
16.9344
Reserved
Reserved
Reserved
12.288
Reserved
16.9344
CPUCLK
64
64
64
64
REFCLK/3
64
64
64
64
ASICCLK
32
32
32
32
REFCLK/6
32
32
32
32
USBCLK
48
48
48
48
REFCLK/4
48
48
48
48
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MCSEL
H
M
L
MCCLK
12 MHz
38.4 MHz
19.2 MHz
Table 2. Select Function for MC Clock
MCCLK if VIDSEL = M and AUDSEL = M
REFCLK/16
REFCLK/5
REFCLK/10
UNIT
MHz
MHz
MHz
3