CD74HC40105 Datasheet, PDF (6/14 Pages) Texas Instruments – High Speed CMOS Logic 4-Bit x 16-Word FIFO Register

CD74HC40105, CD74HCT40105
DC Electrical Specifications (Continued)
TEST
CONDITIONS
PARAMETER
Three-State Leakage
Current
SYMBOL V_I (V) I_O (mA)
I_OZ V_IL or V_IH V_O =
V_CC or
GND
V_CC
(V)
6
25^oC
-40^oC TO 85^oC -55^oC TO 125^oC
MIN TYP MAX MIN MAX MIN MAX UNITS
-
-
±0.5
-
±5
-
±10
µA
HCT TYPES
High Level Input
Voltage
V_IH
-
-
4.5 to
2
-
-
2
-
2
-
V
5.5
Low Level Input
Voltage
V_IL
-
-
4.5 to
-
-
0.8
-
0.8
-
0.8
V
5.5
High Level Output
V_OH V_IH or V_IL -0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
Low Level Output
Voltage
CMOS Loads
V_OL V_IH or V_IL 0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
4
4.5
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I_I
V_CC and
0
5.5
-
-
±0.1
-
±1
-
±1
µA
GND
Quiescent Device
Current
I_CC
V_CC or
0
GND
5.5
-
-
8
-
80
-
160
µA
Three-State Leakage
I_OZ V_IL or V_IH V_O =
5.5
-
-
±0.5
-
±5
-
±10
µA
Current
V_CC or
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I_CC
(Note)
V_CC
-2.1
-
4.5 to
-
100 360
-
450
-
490
µA
5.5
NOTE: For dual-supply systems theoretical worst case (V_I = 2.4V, V_CC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
OE
0.75
SI, SO
0.4
Dn
0.3
MR
1.5
NOTE:
360µA
mUanxitaLto2a5d^{oiCs.∆ICC}
limit
specified
in
DC
Electrical
Table,
e.g.,
6