CD74HC40105 Datasheet, PDF (1/14 Pages) Texas Instruments – High Speed CMOS Logic 4-Bit x 16-Word FIFO Register

Data sheet acquired from Harris Semiconductor
SCHS222
February 1998
CD74HC40105,
CD74HCT40105
High Speed CMOS Logic
4-Bit x 16-Word FIFO Register
[ /Title
(CD74
HC401
05,
CD74
HCT40
105)
/Sub-
ject
(High
Speed
CMOS
Features
Description
• Independent Asynchronous Inputs and Outputs
• Expandable in Either Direction
• Reset Capability
• Status Indicators on Inputs and Outputs
• Three-State Outputs
• Shift-Out Independent of Three-State Control
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55^oC to 125^oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC
at V_CC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V_IL= 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH
Applications
• Bit-Rate Smoothing
• CPU/Terminal Buffering
• Data Communications
• Peripheral Buffering
• Line Printer Input Buffers
• Auto-Dialers
• CRT Buffer Memories
• Radar Data Acquisition
The Harris CD74HC40105 and CD74HCT40105 are high-
speed silicon-gate CMOS devices that are compatible,
except for “shift-out” circuitry, with the Harris CD40105B.
They are low-power first-in-out (FIFO) “elastic” storage
registers that can store 16 four-bit words. The 40105 is
capable of handling input and output data at different shifting
rates. This feature makes particularly useful as a buffer
between asynchronous systems.
Each work position in the register is clocked by a control flip-
flop, which stores a marker bit. A “1” signifies that the posi-
tion’s data is filled and a “0” denotes a vacancy in that posi-
tion. The control flip-flop detects the state of the preceding
flip-flop and communicates its own status to the succeeding
flip-flop. When a control flip-flop is in the “0” state and sees a
“1” in the preceeding flip-flop, it generates a clock pulse that
transfers data from the preceding four data latches into its
own four data latches and resets the preceding flip-flop to
“0”. The first and last control flip-flops have buffered outputs.
Since all empty locations “bubble” automatically to the input
end, and all valid data ripple through to the output end, the
status of the first control flip-flop (DATA-IN READY) indicates
if the FIFO is full, and the status of the last flip-flop (DATA-
OUT READY) indicates if the FIFO contains data. As the
earliest data are removed from the bottom of the data stack
(the output end), all data entered later will automatically
propagate (ripple) toward the output.
Ordering Information
TEMP. RANGE
PART NUMBER
(^oC)
PACKAGE PKG. NO.
CD74HC40105E
-55 to 125 16 Ld PDIP E16.3
CD74HCT40105E -55 to 125 16 Ld PDIP E16.3
CD74HC40105M
-55 to 125 16 Ld SOIC M16.15
CD74HCT40105M -55 to 125 16 Ld SOIC M16.15
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1998
1
File Number 1834.1