CD74HC40105 Datasheet, PDF (13/14 Pages) Texas Instruments – High Speed CMOS Logic 4-Bit x 16-Word FIFO Register

INPUTS
MASTER
RESET
SHIFT IN
(DATA VALID)
SHIFT OUT
OUTPUTS
INPUT READY
(CLEAR OUT)
(NOTE 6)
OUTPUT READY
(DATA VALID)
≈180ns
(NOTE 7)
SHIFT-OUT PULSES
HAVE NO EFFECT
SHIFT-IN PULSES
HAVE NO EFFECT
≈180ns
(NOTE 8)
INPUTS
DATA IN
(Db)
THREE-STATE
(OUTPUT
ENABLE)
DATA OUT
(NOTE 6)
1 0 1 1 1 0 0 1 1 0 10 1 0 1 0
(UNKNOWN)
1 0 11 1 0
HIGH Z
INVALID
NOTES:
6. Data valid goes to high level in advance of the data out by a maximum of 38ns at V_CC = 4.5V for C_L = 50pF and T_A = 25^oC.
7. At V_CC = 4.5V, ripple time from position 1 to position 16.
8. At V_CC = 4.5V, ripple time from position 16 to position 1.
FIGURE 14. TIMING DIAGRAM FOR THE CD74HC/HCT40105
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