CD74HC40105 Datasheet, PDF(11/14 Page) Texas Instruments – High Speed CMOS Logic 4-Bit x 16-Word FIFO Register

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CD74HC40105 Datasheet, PDF (11/14 Pages) Texas Instruments – High Speed CMOS Logic 4-Bit x 16-Word FIFO Register

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CD74HC40105, CD74HCT40105

Test Circuits and Waveforms (Continued)

trCL

CLOCK

INPUT

90%

10%

tH(H)

tfCL

50%

tH(L)

DATA

INPUT

tSU(H)

tSU(L)

OUTPUT

tREM

VCC

SET, RESET

OR PRESET

tTLH

90%

tPLH

50%

tTHL

90%

50%

10%

tPHL

50pF

VCC

GND

VCC

50%

GND

trCL

CLOCK

INPUT

2.7V

0.3V

tfCL

1.3V

tH(H)

tH(L)

DATA

INPUT

tSU(H)

1.3V

tSU(L)

OUTPUT

tREM

SET, RESET

OR PRESET

tTLH

90%

1.3V

tPLH

1.3V

tTHL

90%

1.3V

10%

tPHL

50pF

GND

FIGURE 7. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

FIGURE 8. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

6ns

OUTPUT

DISABLE

50%

OUTPUT LOW

TO OFF

tPLZ

tPHZ

OUTPUT HIGH

TO OFF

OUTPUTS

ENABLED

90%

10%

90%

6ns

10%

tPZL

tPZH

OUTPUTS

DISABLED

VCC

GND

50%

OUTPUTS

ENABLED

FIGURE 9. HC THREE-STATE PROPAGATION DELAY

WAVEFORM

6ns

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

tPLZ

tPHZ

OUTPUT HIGH

TO OFF

OUTPUTS

ENABLED

2.7

1.3

6ns

0.3

tPZL

GND

10%

90%

tPZH

OUTPUTS

DISABLED

1.3V

OUTPUTS

ENABLED

FIGURE 10. HCT THREE-STATE PROPAGATION DELAY

WAVEFORM

OTHER

INPUTS

TIED HIGH

OR LOW

OUTPUT

DISABLE

IC WITH

THREE-

STATE

OUTPUT

RL = 1kâ¦

50pF

VCC FOR tPLZ AND tPZL

GND FOR tPHZ AND tPZH

NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kâ¦ to

VCC, CL = 50pF.

FIGURE 11. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

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