BQ2018TS-E1 Datasheet, PDF (6/25 Pages) Texas Instruments – Power Minder IC

bq2018
Table 3. WOE Thresholds
WOE_3–1 (hex)
0h
1h
2h
3h
4h
5h
6h
7h*
V_WOE (mV)
n/a
3.840
1.920
1.280
0.960
0.768
0.640
0.549
Table 4. Temperature Steps
Temp
<0°
0–10°
10–20°
20–30°
30–40°
40–50°
50–60°
>60°
Value (hex)
0h
1h
2h
3h
4h
5h
6h
7h
SDR Count Rate
× 1/8
× 1/4
× 1/2
1 count/hr.
×2
×4
×8
× 16
* Default value after POR.
Temperature
The bq2018 has an internal temperature sensor which is
used to set the value in the temperature register
(TMP/CLR) and set the self-discharge count rate value.
The register reports the temperature in 8 steps of 10°C
from <0°C to >60°C as Table 4 specifies. The bq2018 tem-
perature sensor has typical accuracy of ± 2°C at 25°C.
See the TMP/CLR register description for more details.
Clear Register
The host system is responsible for register maintenance.
To facilitate this maintenance, the bq2018 has a Clear
Register (TMP/CLR) designed to reset the specific coun-
ter or register pair to zero. The host system clears a reg-
ister by writing the corresponding register bit to 1. When
the bq2018 completes the reset, the corresponding bit in
the TMP/CLR register is automatically reset to 0, which
saves the host an extra write/read cycle. Clearing the
DTC register clears the STD bit and sets the DTC count
rate to the default value of 1 count per 0.8789s. Clearing
the CTC register clears the STC bit and sets the CTC
count rate to the default value of 1 count per 0.8789s.
Calibration Mode
The system can enable bq2018 V_OS calibration by setting
the calibration bit in the MODE/WOE register (Bit 6) to
1. The bq2018 then enters calibration mode when the
HDQ line is low for greater than 10 seconds and when
the signal between SR1 and SR2 is below V_WOE. Cau-
tion: Take care to ensure that no low-level exter-
nal signal is present between SR1 and SR2 because
this affects the calibration value that the bq2018
calculates.
If HDQ remains low for one hour and |V_SR| < V_WOE for
the entire time, the measured V_OS is latched into the
OFR register, and the calibration bit is reset to zero, indi-
cating to the system that the calibration cycle is com-
plete. Once calibration is complete, the bq2018 enters a
Written by Host to bq2018
CMDR = 73h
Break
LSB
MSB
01 234567
Received by Host from bq2018
LSB
01
Data (OFR) = 65h
2345
MSB
67
1 100 1 1 1 0
MSB
LSB
73h = 0 1 1 1 0 0 1 1
10 10 0 1 10
MSB
LSB
65h = 0 1 1 0 0 1 0 1
TD201801.eps
Figure 4. Typical Communication with the bq2018
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