TMS320DM642_08 Datasheet, PDF (57/176 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processor

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TMS320DM642
Video/Imaging Fixed-Point Digital Signal Processor
SPRS200L – JULY 2002 – REVISED JANUARY 2007
Table 3-4. Peripheral Configuration (PERCFG) Register Selection Bit Descriptions (continued)
BIT
NAME
DESCRIPTION
VP1 Enable bit.
Determines whether the VP1 peripheral is enabled or disabled.
5
VP1EN
0 = VP1 is disabled, and the module is powered down (default).
(This feature allows power savings by disabling the peripheral when not in use.)
1 = VP1 is enabled.
VP0 Enable bit.
Determines whether the VP0 peripheral is enabled or disabled.
4
VP0EN
0 = VP0 is disabled, and the module is powered down (default).
(This feature allows power savings by disabling the peripheral when not in use.)
1 = VP0 is enabled.
Inter-integrated circuit 0 (I2C0) enable bit.
Selects whether I2C0 peripheral is enabled or disabled (default).
3
I2C0EN
0 = I2C0 is disabled, and the module is powered down (default).
1 = I2C0 is enabled.
Video Port 1 (VP1) lower data pins vs. McBSP1 enable bit.
Selects whether VP1 peripheral lower-data pins or the McBSP1 peripheral is enabled.
0 = VP1 lower-data pins are enabled and function (if VP1EN=1), McBSP1 is disabled; the remaining VP1
2
MCBSP1EN
upper-data pins are dependent on the MCASP0EN bit and the VP1EN bit settings.
1 = McBSP1 is enabled, VP1 lower-data pin functions are disabled (default).
For a graphic (logic) representation of this Peripheral Configuration (PERCFG) Register selection bit and
the signal pins controlled/selected, see Figure 3-2.
Video Port 0 (VP0) lower data pins vs. McBSP0 enable bit.
Selects whether VP0 peripheral lower-data pins or the McBSP1 peripheral is enabled.
0 = VP0 lower-data pins are enabled and function (if VP0EN=1), McBSP0 is disabled; the remaining VP0
1
MCBSP0EN
upper-data pins are dependent on the MCASP0EN bit and the VP1EN bit settings.
1 = McBSP0 is enabled, VP0 lower-data pin functions are disabled (default).
For a graphic (logic) representation of this Peripheral Configuration (PERCFG) Register selection bit and
the signal pins controlled/selected, see Figure 3-2.
McASP0 vs. VP0/VP1 upper-data pins select bit.
Selects whether the McASP0 peripheral or the VP0 and VP1 upper-data pins are enabled.
0 = McASP0 is disabled; VP0 and VP1 upper-data pins are enabled; and the VP0 and VP1lower-data
0
MCASP0EN
pins are dependent on the MCBSP0EN and VP0EN, and MCSBP1EN and VP1EN bits, respectively.
1 = McASP0 is enabled; VP0 and VP1 upper-data pins are disabled; and the VP0 and VP1lower-data
pins are dependent on the MCBSP0EN and VP0EN, and MCSBP1EN andVP1EN bits, respectively.
For a graphic (logic) representation of this Peripheral Configuration (PERCFG) Register selection bit and
the signal pins controlled/selected, see Figure 3-2.
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Device Configurations
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