TMS320DM642_08 Datasheet, PDF (1/176 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processor

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TMS320DM642
Video/Imaging Fixed-Point Digital Signal Processor
SPRS200L – JULY 2002 – REVISED JANUARY 2007
1 TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor
1.1 Features
• High-Performance Digital Media Processor
– 2-, 1.67-, 1.39-ns Instruction Cycle Time
– 500-, 600-, 720-MHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– 4000, 4800, 5760 MIPS
– Fully Software-Compatible With C64x™
• VelociTI.2™ Extensions to VelociTI™
Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x™ DSP Core
– Eight Highly Independent Functional Units
With VelociTI.2™ Extensions:
• Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
• Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
– Load-Store Architecture With Non-Aligned
Support
– 64 32-Bit General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
• Instruction Set Features
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– 8-Bit Overflow Protection
– Bit-Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
– VelociTI.2™ Increased Orthogonality
• L1/L2 Memory Architecture
– 128K-Bit (16K-Byte) L1P Program Cache
(Direct Mapped)
– 128K-Bit (16K-Byte) L1D Data Cache (2-Way
Set-Associative)
– 2M-Bit (256K-Byte) L2 Unified Mapped
RAM/Cache (Flexible RAM/Cache
Allocation)
• Endianess: Little Endian, Big Endian
• 64-Bit External Memory Interface (EMIF)
– Glueless Interface to Asynchronous
Memories (SRAM and EPROM) and
Synchronous Memories (SDRAM, SBSRAM,
ZBT SRAM, and FIFO)
– 1024M-Byte Total Addressable External
Memory Space
• Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
• 10/100 Mb/s Ethernet MAC (EMAC)
– IEEE 802.3 Compliant
– Media Independent Interface (MII)
– 8 Independent Transmit (TX) Channels and
1 Receive (RX) Channel
• Management Data Input/Output (MDIO)
• Three Configurable Video Ports
– Providing a Glueless I/F to Common Video
Decoder and Encoder Devices
– Supports Multiple Resolutions/Video Stds
• VCXO Interpolated Control Port (VIC)
– Supports Audio/Video Synchronization
• Host-Port Interface (HPI) [32-/16-Bit]
• 32-Bit/66-MHz, 3.3-V Peripheral Component
Interconnect (PCI) Master/Slave Interface
Conforms to PCI Specification 2.2
• Multichannel Audio Serial Port (McASP)
– Eight Serial Data Pins
– Wide Variety of I²S and Similar Bit Stream
Format
– Integrated Digital Audio I/F Transmitter
Supports S/PDIF, IEC60958-1, AES-3,
CP-430 Formats
• Inter-Integrated Circuit (I²C Bus™)
• Two Multichannel Buffered Serial Ports
• Three 32-Bit General-Purpose Timers
• Sixteen General-Purpose I/O (GPIO) Pins
• Flexible PLL Clock Generator
• IEEE-1149.1 (JTAG) Boundary-
Scan-Compatible
• 548-Pin Ball Grid Array (BGA) Package
(GDK and ZDK Suffixes), 0.8-mm Ball Pitch
• 548-Pin Ball Grid Array (BGA) Package
(GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
• 0.13-µm/6-Level Cu Metal Process (CMOS)
• 3.3-V I/O, 1.2-V Internal (-500)
• 3.3-V I/O, 1.4-V Internal (A-500, A-600, -600,
-720)
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Instruments semiconductor products and disclaimers thereto appears at the end of this document.
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I²C Bus is a trademark of Philips Electronics N.V..
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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