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MSP430X241X Datasheet, PDF (55/98 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (UART mode)
PARAMETER
TEST CONDITIONS
VCC
MIN TYP MAX UNIT
fUSCI
USCI input clock frequency
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
fSYSTEM MHz
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
2.2 V /3 V
1 MHz
UART receive deglitch time
tτ
(see Note 1)
2.2 V
3V
50 150 600 ns
50 100 600 ns
NOTE 1: Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI master mode) (see Figure 27 and Figure 28)
PARAMETER
TEST CONDITIONS
VCC
MIN MAX UNIT
fUSCI
USCI input clock frequency
SMCLK, ACLK
Duty cycle = 50% ± 10%
fSYSTEM MHz
tSU,MI
SOMI input data setup time
2.2 V
110
ns
3V
75
tHD,MI
SOMI input data hold time
2.2 V
0
ns
3V
0
tVALID,MO
SIMO output data valid time
UCLK edge to SIMO valid;
CL = 20 pF
2.2 V
3V
30
ns
20
NOTE 2:
fUCxCLK
=
1
2tLO∕HI
with
tLO∕HI
≥
max(tVALID,MO(USCI)
+
tSU,SI(Slave),
tSU,MI(USCI)
+
t VALID,SO(Slave)) .
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
USCI (SPI slave mode) (see Figure 29 and Figure 30)
PARAMETER
TEST CONDITIONS
VCC
MIN TYP
tSTE,LEAD
STE lead time,
STE low to clock
2.2 V/3 V
50
tSTE,LAG
STE lag time,
Last clock to STE high
2.2 V/3 V
10
tSTE,ACC
STE access time,
STE low to SOMI data out
2.2 V/3 V
50
tSTE,DIS
STE disable time,
STE high to SOMI high impedance
2.2 V/3 V
50
tSU,SI
SIMO input data setup time
2.2 V
20
3V
15
tHD,SI
SIMO input data hold time
2.2 V
10
3V
10
UCLK edge to SOMI valid;
2.2 V
75
tVALID,SO
SOMI output data valid time
CL = 20 pF
3V
50
NOTE 3:
fUCxCLK
=
1
2tLO∕HI
with
tLO∕HI
≥
max(tVALID,MO(Master)
+
tSU,SI(USCI),
tSU,MI(Master)
+
tVALID,SO(USCI))
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
MAX UNIT
ns
ns
ns
ns
ns
ns
110
ns
75
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