MSP430X241X Datasheet, PDF (14/98 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0x0FFFF to 0x0FFC0.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. If the reset
vector (0x0FFFE) contains 0xFFFF (e.g., flash is not programmed), the CPU enters LPM4 after power-up.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power-up
External Reset
Watchdog
Flash Key Violation
PC out of range (see Note 1)
PORIFG
WDTIFG
RSTIFG
KEYV (see Note 2)
Reset
0x0FFFE
31, highest
NMI
Oscillator Fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG (see Notes 2 and 6)
(Non)maskable
(Non)maskable
0x0FFFC
30
(Non)maskable
Timer_B7
TBCCR0 CCIFG
(see Note 3)
Maskable
0x0FFFA
29
Timer_B7
TBCCR1 to TBCCR6 CCIFGs, TBIFG
(see Notes 2 and 3)
Maskable
0x0FFF8
28
Comparator_A+
CAIFG
Maskable
0x0FFF6
27
Watchdog timer+
WDTIFG
Maskable
0x0FFF4
26
Timer_A3
TACCR0 CCIFG (see Note 3)
Maskable
0x0FFF2
25
Timer_A3
TACCR1 CCIFG
TACCR2 CCIFG
TAIFG (see Notes 2 and 3)
Maskable
0x0FFF0
24
USCI_A0/USCI_B0 receive
USCI_B0 I2C status
UCA0RXIFG, UCB0RXIFG
(see Notes 2 and 4)
Maskable
0x0FFEE
23
USCI_A0/USCI_B0 transmit
USCI_B0 I2C receive/transmit
UCA0TXIFG, UCB0TXIFG
(see Note 2 and 4)
Maskable
0x0FFEC
22
ADC12
ADC12IFG (see Notes 2 and 3)
Maskable
0x0FFEA
21
0x0FFE8
20
I/O port P2 (eight flags)
P2IFG.0 to P2IFG.7 (see Notes 2 and 3)
Maskable
0x0FFE6
19
I/O port P1 (eight flags)
P1IFG.0 to P1IFG.7 (see Notes 2 and 3)
Maskable
0x0FFE4
18
USCI_A0/USCI_B1 receive
USCI_B1 I2C status
UCA1RXIFG, UCB1RXIFG
(see Notes 2 and 4)
Maskable
0x0FFE2
17
USCI_A1/USCI_B1 transmit
USCI_B1 I2C receive/transmit
UCA1TXIFG, UCB1TXIFG
(see Notes 2 and 5)
Maskable
0x0FFE0
16
DMA
DMA0IFG, DMA1IFG, DMA2IFG
(see Notes 2 and 3)
Maskable
0x0FFDE
15
DAC12
DAC12_0IFG, DAC12_1IFG
(see Notes 2 and 3)
Maskable
0x0FFDC
14
Reserved (see Notes 7 and 8)
Reserved
0x0FFDA to
0x0FFC0
13 to 0,
lowest
NOTES:
1. A reset is executed if the CPU tries to fetch instructions from within the module register memory address range (0x00000 to 0x001FF)
or from within unused address ranges.
2. Multiple source flags.
3. Interrupt flags are located in the module.
4. In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
5. In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
6. (Non)maskable: The individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot.
7. The address 0x0FFBE is used as bootstrap loader security key (BSLSKEY).
A 0x0AA55 at this location disables the BSL completely.
A zero disables the erasure of the flash if an invalid password is supplied.
8. The interrupt vectors at addresses 0x0FFDA to 0x0FFC0 are not used in this device and can be used for regular program code if
necessary.
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