MSP430F543X_10 Datasheet, PDF (55/99 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430F543x, MSP430F541x
www.ti.com
USCI (UART Mode) - recommended operating conditions
PARAMETER
CONDITIONS
f_USCI
USCI input clock frequency
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
f_BITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
SLAS612C – AUGUST 2009 – REVISED MARCH 2010
V_CC
MIN TYP MAX UNIT
f_SYSTEM MHz
1 MHz
USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
t_t
UART receive deglitch time⁽¹⁾
TEST CONDITIONS
V_CC
2.2 V
3V
MIN TYP
50
50
MAX
600
600
UNIT
ns
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their width should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode) - recommended operating conditions
PARAMETER
CONDITIONS
V_CC
f_USCI
USCI input clock frequency
Internal: SMCLK, ACLK
Duty cycle = 50% ± 10%
MIN TYP MAX UNIT
f_SYSTEM MHz
USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note ⁽¹⁾, Figure 11 and Figure 12)
f_USCI
PARAMETER
USCI input clock frequency
TEST CONDITIONS
SMCLK, ACLK
Duty cycle = 50% ± 10%
V_CC
MIN TYP MAX UNIT
f_SYSTEM MHz
t_SU,MI
SOMI input data setup time
2.2 V
65
ns
3V
50
t_HD,MI
SOMI input data hold time
2.2 V
0
ns
3V
0
t_VALID,MO SIMO output data valid time⁽²⁾
UCLK edge to SIMO valid,
C_L = 20 pF
2.2 V
3V
25
ns
20
t_HD,MO
SIMO output data hold time⁽³⁾
C_L = 20 pF
2.2 V
3V
ns
(1) f_UCxCLK = 1/2t_LO/HI with tL_O/HI ≥ max(t_{VALID,MO(USCI)} + t_SU,SI(Slave), t_SU,MI(USCI) + t_{VALID,SO(Slave)}).
For the slave's parameters t_SU,SI(Slave) and t_{VALID,SO(Slave)} refer to the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 11 and Figure 12.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams in
Figure 11 and Figure 12.
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
55