MSP430F543X_10 Datasheet, PDF (54/99 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430F543x, MSP430F541x
SLAS612C – AUGUST 2009 – REVISED MARCH 2010
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Wake-up from Low Power Modes
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
t_WAKE-UP-
FAST
PARAMETER
Wake-up time from
LPM2, LPM3, or LPM4
to active mode⁽¹⁾
TEST CONDITIONS
PMMCOREV = SVSMLRRL = 2
SVSLFP = 1
V_CC
MIN
2.2/3.0 V
t_WAKE-UP-
SLOW
Wake-up time from
LPM2, LPM3 or LPM4 to
active mode⁽²⁾
PMMCOREV = SVSMLRRL = 2
SVSLFP = 0
2.2/3.0 V
TYP MAX UNIT
5 µs
150
µs
(1) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVS_L) and low side monitor (SVM_L). Fastest wakeup times are possible with SVS_Land SVM_L in full
performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVS_Land SVM_L while
operating in LPM2, LPM3, and LPM4. Please refer to the Power Management Module and Supply Voltage Supervisor chapter in the
MSP430x5xx Family User's Guide (SLAU208).
(2) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVS_L) and low side monitor (SVM_L). In this case, the SVS_Land SVM_L are in normal mode (low current)
mode when operating in AM, LPM0, and LPM1. Various options are available for SVS_Land SVM_L while operating in LPM2, LPM3, and
LPM4. Please refer to the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx Family User's Guide
(SLAU208).
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Internal: SMCLK, ACLK
f_TA
Timer_A input clock frequency
External: TACLK
Duty cycle = 50% ± 10%
V_CC
1.8 V/
3.0 V
MIN TYP
t_TA,cap
Timer_A capture timing
All capture inputs.
Minimum pulse width required for
capture.
1.8 V/
3.0 V
20
MAX UNIT
25 MHz
ns
Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Internal: SMCLK, ACLK
f_TB
Timer_B input clock frequency
External: TBCLK
Duty cycle = 50% ± 10%
V_CC
1.8 V/
3.0 V
MIN TYP
t_TB,cap
Timer_B capture timing
All capture inputs.
Minimum pulse width required for
capture.
1.8 V/
3.0 V
20
MAX UNIT
25 MHz
ns
54
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