TMS320R2811_11 Datasheet, PDF (51/154 Pages) Texas Instruments – Digital Signal Processors

Functional Overview
Table 3−15. R281x Low-Power Modes
MODE
Normal
LPM(1:0)
X,X
IDLE
0,0
OSCCLK
on
on
CLKIN
on
on
SYSCLKOUT
on
on‡
EXIT†
−
XRS,
WDINT,
Any Enabled Interrupt,
XNMI
Debugger§
on
STANDBY
0,1
off
off
(watchdog still running)
XRS,
WDINT,
XINT1,
XNMI,
T1/2/3/4CTRIP,
C1/2/3/4/5/6TRIP,
SCIRXDA,
SCIRXDB,
CANRX,
Debugger§
off
HALT
1,X
(oscillator and PLL turned off,
off
off
watchdog not functional)
XRS,
XNMI,
Debugger§
† _{The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, will exit the}
low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise the IDLE mode will not
be exited and the device will go back into the indicated low power mode.
‡ _{The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the core (SYSCLKOUT) is still functional}
while on the 24x/240x the clock is turned off.
§ _{On the C28x, the JTAG port can still function even if the core clock (CLKIN) is turned off.}
The various low-power modes operate as follows:
IDLE Mode:
STANDBY Mode:
HALT Mode:
This mode is exited by any enabled interrupt or an XNMI that is
recognized by the processor. The LPM block performs no tasks during
this mode as long as the LPMCR0(LPM) bits are set to 0,0.
All other signals (including XNMI) will wake the device from STANDBY
mode if selected by the LPMCR1 register. The user will need to select
which signal(s) will wake the device. The selected signal(s) are also
qualified by the OSCCLK before waking the device. The number of
OSCCLKs is specified in the LPMCR0 register.
Only the XRS and XNMI external signals can wake the device from
HALT mode. The XNMI input to the core has an enable/disable bit.
Hence, it is safe to use the XNMI signal for this function.
NOTE: The low-power modes do not affect the state of the output pins (PWM pins included). They will be
in whatever state the code left them when the IDLE instruction was executed.
52 SPRS257C
June 2004 − Revised June 2006