TMS320R2811_11 Datasheet, PDF (128/154 Pages) Texas Instruments – Digital Signal Processors

Electrical Specifications
Table 6−40. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)^{†‡§}
MIN
MAX
UNIT
td(HL-HiZ)
Delay time, XHOLD low to Hi-Z on all Address, Data, and Control
4tc(XTIM)+tc(XCO) ns
td(HL-HAL)
Delay time, XHOLD low to XHOLDA low
4tc(XTIM+2tc(XCO) ns
td(HH-HAH)
Delay time, XHOLD high to XHOLDA high
4tc(XTIM) ns
td(HH-BV)
Delay time, XHOLD high to Bus valid
6tc(XTIM) ns
† _{When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance state.}
‡ _{The state of XHOLD is latched on the rising edge of XTIMCLK.}
§ _{After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions will occur with respect to the rising edge of XCLKOUT. Thus,}
for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier than the maximum value specified.
XCLKOUT
(1/2 XTIMCLK)
XHOLD
XHOLDA
XR/W,
XZCS0AND1,
XZCS2,
XZCS6AND7
XA[18:0]
XD[15:0]
td(HL-HAL)
td(HL-HiZ)
Valid
ÁÁÁÁ
Valid
See Note A
td(HH-HAH)
td(HH-BV)
High-Impedance
High-Impedance
High-Impedance
ÁÁ_Valid
ÁÁÁÁÁÁÁÁ _{See Note B}
NOTES:
A All pending XINTF accesses are completed.
B Normal XINTF operation resumes.
Figure 6−34. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
June 2004 − Revised June 2006
SPRS257C 129