TMS320DM641_05 Datasheet, PDF (51/179 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processors

Pin Assignments
Table 1−6. Terminal Functions (Continued)
SIGNAL
NAME
DM641
DM640 ^TYPE†
IPD/
IPU^‡
ETHERNET MAC (EMAC)
DESCRIPTION
MRCLK
MCRS
MRXER
MRXDV
MRXD3
MRXD2
MRXD1
MRXD0
MTCLK
MCOL
MTXEN
MTXD3
MTXD2
MTXD1
MTXD0
G1
G1
I
H3
H3
I
G2
G2
I
J4
J4
I
H2
H2
I
J3
J3
I
J1
J1
I
K4
K4
I
L4
L4
I
K2
K2
I
L3
L3
O/Z
L2
L2
O/Z
M4
M4
O/Z
M2
M2
O/Z
M3
M3
O/Z
EMAC Media Independent I/F (MII) data, clocks, and control pins for
Transmit/Receive.
MII transmit clock (MTCLK),
Transmit clock source from the attached PHY.
MII transmit data (MTXD[3:0]),
Transmit data nibble synchronous with transmit clock (MTCLK).
MII transmit enable (MTXEN),
This signal indicates a valid transmit data on the transmit data pins
(MTDX[3:0]).
MII collision sense (MCOL)
Assertion of this signal during half-duplex operation indicates network
collision.
During full-duplex operation, transmission of new frames will not begin if
this pin is asserted.
MII carrier sense (MCRS)
Indicates a frame carrier signal is being received.
MII receive data (MRXD[3:0]),
Receive data nibble synchronous with receive clock (MRCLK).
MII receive clock (MRCLK),
Receive clock source from the attached PHY.
MII receive data valid (MRXDV),
This signal indicates a valid data nibble on the receive data pins
(MRDX[3:0]).
MII receive error (MRXER),
Indicates reception of a coding error on the receive data.
MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) CONTROL
AHCLKX0
AC12 AC12 I/O/Z IPD McASP0 transmit high-frequency master clock (I/O/Z).
AFSX0
AD12 AD12 I/O/Z IPD McASP0 transmit frame sync or left/right clock (LRCLK) (I/O/Z).
ACLKX0
AB13 AB13 I/O/Z IPD McASP0 transmit bit clock (I/O/Z).
AMUTE0
AC13 AC13 O/Z
IPD McASP0 mute output (O/Z).
AMUTEIN0
AD13 AD13 I/O/Z IPD McASP0 mute input (I/O/Z).
AHCLKR0
AB14 AB14 I/O/Z IPD McASP0 receive high-frequency master clock (I/O/Z).
AFSR0
AC14 AC14 I/O/Z IPD McASP0 receive frame sync or left/right clock (LRCLK) (I/O/Z).
ACLKR0
AD14 AD14 I/O/Z IPD McASP0 receive bit clock (I/O/Z).
MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) DATA
AXR0[3]
AE11 AE11
AXR0[2]
AXR0[1]
AC10
AD10
AC10
AD10
I/O/Z
IPD McASP0 TX/RX data pins [3:0] (I/O/Z).
AXR0[0]
AC9 AC9
† _{I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground}
‡ _{IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite}
supply rail, a 1-kΩ resistor should be used.)
§ _{These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.}
June 2003 − Revised October 2005
SPRS222E
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