TMS320DM641_05 Datasheet, PDF (40/179 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processors

Pin Assignments
STCLK
VP0CLK0
VP0CLK1
VP0CTL0
VP0CTL1
VP0CTL2
Timing and
Control Logic
VP0D[0]/CLKX0
VP0D[1]/FSX0
VP0D[2]/DX0
VP0D[3]/CLKS0
Capture/Display
Buffer
(2560 Bytes)
VP0D[4]/DR0
VP0D[5]/FSR0
VP0D[6]/CLKR0
VP0D[7]
Channel A^†
Video Port 0 (VP0)
† _{Channel A supports: BT.656 (8-bit) display pipeline mode and BT.656 (8-bit) capture pipeline mode [TSI (8-bit) capture}
pipeline mode].
Figure 1−6. Peripheral Signals (Continued)
40 SPRS222E
June 2003 − Revised October 2005