TMS320DM641_05 Datasheet, PDF (115/179 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processors

External Memory Interface (EMIIF)
WRITE
AECLKOUTx
ACEx
ABE[3:0]
AEA[22:14]
AEA[12:3]
AEA13
AED[31:0]
1
2
2
4
3
BE1
BE2
BE3
BE4
4
5
Bank
4
5
Column
4
5
9
9
10
D1
D2
D3
D4
AAOE/ASDRAS/ASOE^†
AARE/ASDCAS/ASADS/
ASRE^†
AAWE/ASDWE/ASWE^†
8
8
11
11
14
14
APDT^‡
† _{AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,}
respectively, during SDRAM accesses.
‡ _{APDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For APDT write,}
data is not driven (in High-Z). The PDTWL field in the PDT control register (PDTCTL) configures the latency of the APDT signal with respect to
the data phase of a write transaction. The latency of the APDT signal for a write transaction can be programmed to 0, 1, 2, or 3 by setting PDTWL
to 00, 01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in Figure 4−25.
Figure 4−25. SDRAM Write Command for EMIFA
June 2003 − Revised October 2005
SPRS222E 115