THS1230 Datasheet, PDF (5/22 Pages) Texas Instruments – 3.3-V, 12-BIT, 30 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH POWER DOWN

THS1230
www.ti.com
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (AV_DD = DV_DD = 3.3 V, f_s = 30 MHz/50% duty cycle, MODE = 1, 1-V input span,
internal reference, T_min to T_max) (unless otherwise noted)
DIGITAL INPUTS AND OUTPUTS (ALL SUPPLIES = 3.3 V)
PARAMETER
TEST CONDITION
MIN TYP
MAX UNIT
DIGITAL INPUTS
V_IH
High level input voltage
V_IL
Low level input voltage
I_IH
High level input current
I_IL
Low level input current
C_i
Input capacitance
DIGITAL OUTPUTS
All other inputs
CLK
All other inputs
CLK
0.8 × DV_DD
0.8 × AV_DD
V
0.2 × DV_DD
V
0.2 × AV_DD
1 µA
–1 µA
5
pF
V_OH
High level output voltage
V_OL
Low level output voltage
High impedance output current
I_load = 50 µA
I_load = –50 µA
DV_DD–0.4
V
0.4
±1 µA
t_r/t_f
Rise/fall time
ANALOG INPUTS
C_L = 10 pF
4.5
ns
C_i
t_d(ap)
Switched input capacitance
Aperture delay time
Aperture uncertainty (jitter)
6
pF
2
ns
2
ps
DC leakage current (input = ±FS)
10
µA
POWER SUPPLY (CLK = 30 MHz)
XV_DD
I_DD
I_(analog)
I_(digital)
I_I(standby)
t_(PU)
Supply voltage (all supplies)
Supply current active - total
Supply current active - analog
Supply current active - digital
Standby supply current
Power-up time for references from standby
CLK = 0 MHz
1 µF Bypass ⁽¹⁾
10 µF Bypass ⁽¹⁾
3
3.3
48
35
13
770
6.2
3.6 V
66
mA
10 µA
µs
ms
t_(PUconv)
P_D
Power-up time for valid ADC conversions
Power dissipation
See Note ⁽²⁾
See Note ⁽³⁾
See Note ⁽⁴⁾
720
ns
168
220
mW
188
P_D(STBY)
PSRR
Standby power dissipation
Power supply rejection ratio
CLK = 0 MHz
36 µW
±0.1
%FS
(1) Time for reference to recover to 1% of its final voltage level.
(2) Time for ADC conversions to be accurate to within 0.1% of fullscale, INT ckts.
(3) Clock = 30 MHz, AIN+ and AIN– at Common Mode or 1.65 V DC.
(4) Clock = 30 MHz, fin = 3.58 MHz at –1 dBFS.
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