THS1230 Datasheet, PDF (13/22 Pages) Texas Instruments – 3.3-V, 12-BIT, 30 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH POWER DOWN

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AIN+
AIN−
THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
REFT
+1
SAMPLE
−1 ^AND
HOLD
VP+
VP−
ADC
CORE
REFB
Figure 15. Analog Input Signal Flow
Sample and Hold
The differential sample and hold processes A_IN with respect to the voltages applied to the REFT and REFB pins,
to give a differential output (VP+) – (VP–) = VP given by:
• VP = (AIN+) – ( AIN–)
Analog-to-Digital Converter
No matter what operating configuration is chosen, VP is digitized against ADC reference voltages V_REFT and
V_REFB. The V_REFT and V_REFB voltages set the analog input span limits FS+ and FS–, respectively. Any voltages at
AIN greater than REFT or less than REFB causes ADC over-range, which is signaled by OVR going high when
the conversion result is output.
Analog Input
A first-order approximation for the equivalent analog input circuit of the THS1230 is shown in Figure 16. The
equivalent input capacitance C_I is 5 pF typical. The input must charge/discharge this capacitance within the
sample period of one half of a clock cycle. When a full-scale voltage step is applied, the input source provides
the charging current through the switch resistance R_SW (200 Ω) of S1 and quickly settles. In this case the input
impedance is low. Alternatively, when the source voltage equals the value previously stored on C_I, the hold
capacitor requires no input current and the equivalent input impedance is very high.
THS1230
RS
RSW
RS
RSW
VS+
VS −
VCM
+
_
CI
CI
VCM
+
_
Figure 16. Simplified Equivalent Input Circuit
To maintain the frequency performance outlined in the specifications, the total source impedance should be
limited to the following equation with f_CLK = 30 MHz, C_I = 5 pF, R_SW = 200 Ω:
RS t _2fCLK
1
CI
In(256) ^–RSW
So, for applications running at a lower f_CLK, the total source resistance can increase proportionally.
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