THS1230 Datasheet, PDF (12/22 Pages) Texas Instruments – 3.3-V, 12-BIT, 30 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH POWER DOWN

THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
MODE
0
1
2
3
Table 1. Input Modes of Operation
CON1
0
0
1
1
CON0
0
1
0
1
MODE OF OPERATION
Device powered down
Differential mode × 1
Differential mode × 0.5
Not used
Modes 1 and 2 are shown in Figure 14.
www.ti.com
AIN−
AIN+
4095
1V
0
MODE 1, CON[1:0] = 01
4095
AIN−
2V
AIN+
0
MODE 2, CON[1:0] = 10
Figure 14. Input Mode Configurations
The gain of the sample and hold changes with the CON1 and the CON0 inputs. Table 2 shows the gain of the
sample and hold and the levels applied at the AIN+ and AIN– analog inputs for Mode 1 and Mode 2. The
common mode level for the two analog inputs is at AVDD/2.
MODE
1
2
CON1
0
1
Table 2. Input Mode Switching
CON0
1
0
(AIN+) – (AIN–)
MIN
–1 V
–2 V
(AIN+) – (AIN–)
MAX
1V
2V
S/H GAIN
×1
×0.5
Table 2 assumes that the delta in ADC reference voltages V_REFT and V_REFB is set to 1 V, i.e., V_REFT – V_REFB = 1
V. Note that V_REFB and V_REFT can be set externally, which will scale the numbers given in this table.
The user-chosen operating configuration and reference voltages determine what input signal voltage range the
THS1230 can handle.
The following sections explain both the internal signal flow of the device and how the input signal span is related
to the ADC reference voltages, as well as the ways in which the ADC reference voltages can be buffered
internally or externally applied.
Signal Processing Chain (Sample and Hold, ADC)
Figure 15 shows the signal flow through the sample and hold unit and the PGA to the ADC core.
12